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| author | Michael Ellerman <mpe@ellerman.id.au> | 2015-03-28 21:35:16 +1100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2015-03-28 22:03:40 +1100 |
| commit | 529d235a0e190ded1d21ccc80a73e625ebcad09b (patch) | |
| tree | c807f7526f29b79a7ce0b233daf8a1c3030d8dd0 /arch/powerpc/kernel/entry_64.S | |
| parent | c03e73740d24fbe990291cd9ac2d6ae0d95b975f (diff) | |
| download | linux-529d235a0e190ded1d21ccc80a73e625ebcad09b.tar.gz | |
powerpc: Add a proper syscall for switching endianness
We currently have a "special" syscall for switching endianness. This is
syscall number 0x1ebe, which is handled explicitly in the 64-bit syscall
exception entry.
That has a few problems, firstly the syscall number is outside of the
usual range, which confuses various tools. For example strace doesn't
recognise the syscall at all.
Secondly it's handled explicitly as a special case in the syscall
exception entry, which is complicated enough without it.
As a first step toward removing the special syscall, we need to add a
regular syscall that implements the same functionality.
The logic is simple, it simply toggles the MSR_LE bit in the userspace
MSR. This is the same as the special syscall, with the caveat that the
special syscall clobbers fewer registers.
This version clobbers r9-r12, XER, CTR, and CR0-1,5-7.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/entry_64.S')
| -rw-r--r-- | arch/powerpc/kernel/entry_64.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index d180caf2d6de..afbc20019c2e 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -356,6 +356,11 @@ _GLOBAL(ppc64_swapcontext) bl sys_swapcontext b .Lsyscall_exit +_GLOBAL(ppc_switch_endian) + bl save_nvgprs + bl sys_switch_endian + b .Lsyscall_exit + _GLOBAL(ret_from_fork) bl schedule_tail REST_NVGPRS(r1) |