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authorPaul Mackerras <paulus@ozlabs.org>2017-09-11 15:29:45 +1000
committerPaul Mackerras <paulus@ozlabs.org>2017-11-01 15:36:06 +1100
commit8dc6cca556e4126f77b71cf8e0c45ccc78d1d213 (patch)
treee65a18826f1c90e7548cffec5c97cae7a45e9567 /arch/powerpc/kvm/book3s_exports.c
parent3e8f150a3bc30214c15e5f8d27e4b2d904bd929e (diff)
downloadlinux-8dc6cca556e4126f77b71cf8e0c45ccc78d1d213.tar.gz
KVM: PPC: Book3S HV: Don't rely on host's page size information
This removes the dependence of KVM on the mmu_psize_defs array (which stores information about hardware support for various page sizes) and the things derived from it, chiefly hpte_page_sizes[], hpte_page_size(), hpte_actual_page_size() and get_sllp_encoding(). We also no longer rely on the mmu_slb_size variable or the MMU_FTR_1T_SEGMENTS feature bit. The reason for doing this is so we can support a HPT guest on a radix host. In a radix host, the mmu_psize_defs array contains information about page sizes supported by the MMU in radix mode rather than the page sizes supported by the MMU in HPT mode. Similarly, mmu_slb_size and the MMU_FTR_1T_SEGMENTS bit are not set. Instead we hard-code knowledge of the behaviour of the HPT MMU in the POWER7, POWER8 and POWER9 processors (which are the only processors supported by HV KVM) - specifically the encoding of the LP fields in the HPT and SLB entries, and the fact that they have 32 SLB entries and support 1TB segments. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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