diff options
| author | Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:06:51 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-06 14:29:23 +0100 |
| commit | 2b2dbc2f94e55c940e1eed70706f363aa94373b0 (patch) | |
| tree | 98b829f5994e730895ad0fa6f0dbaec40b69d014 /drivers/clk/tegra/cvb.h | |
| parent | f7ebf8874c2abb12be786fe73734ba47c87ff123 (diff) | |
| download | linux-2b2dbc2f94e55c940e1eed70706f363aa94373b0.tar.gz | |
clk: tegra: dfll: add CVB tables for Tegra210
Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.
The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/cvb.h')
| -rw-r--r-- | drivers/clk/tegra/cvb.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index bcf15a089b93..91a1941c21ef 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data { u32 tune0_low; u32 tune0_high; u32 tune1; + unsigned int tune_high_min_millivolts; }; struct cvb_table { |