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| author | Julien Masson <jmasson@baylibre.com> | 2019-08-22 16:43:41 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2019-08-22 17:54:05 +0200 |
| commit | 528a25d040bc2123fe5a9f8697a60f8bff40af0a (patch) | |
| tree | 506b2ee5efb635bef3ab47a7cd8e2355d43af74a /drivers/gpu/drm/meson/meson_vpp.c | |
| parent | ade925995b172f1d7410d1c665b2f47c5e99bef0 (diff) | |
| download | linux-528a25d040bc2123fe5a9f8697a60f8bff40af0a.tar.gz | |
drm: meson: use match data to detect vpu compatibility
This patch introduce new enum which contains all VPU family (GXBB,
GXL, GXM and G12A).
This enum is used to detect the VPU compatible with the device.
We only need to set .data to the corresponding enum in the device
table, no need to check .compatible string anymore.
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87imqpz21w.fsf@masson.i-did-not-set--mail-host-address--so-tickle-me
Diffstat (limited to 'drivers/gpu/drm/meson/meson_vpp.c')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_vpp.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c index 1429f3be6028..154837688ab0 100644 --- a/drivers/gpu/drm/meson/meson_vpp.c +++ b/drivers/gpu/drm/meson/meson_vpp.c @@ -91,20 +91,20 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv, void meson_vpp_init(struct meson_drm *priv) { /* set dummy data default YUV black */ - if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); - else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) { + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { writel_bits_relaxed(0xff << 16, 0xff << 16, priv->io_base + _REG(VIU_MISC_CTRL1)); writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, priv->io_base + _REG(VPP_DOLBY_CTRL)); writel_relaxed(0x1020080, priv->io_base + _REG(VPP_DUMMY_DATA1)); - } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) + } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); /* Initialize vpu fifo control registers */ - if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, priv->io_base + _REG(VPP_OFIFO_SIZE)); else @@ -113,7 +113,7 @@ void meson_vpp_init(struct meson_drm *priv) writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4), priv->io_base + _REG(VPP_HOLD_LINES)); - if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { /* Turn off preblend */ writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, priv->io_base + _REG(VPP_MISC)); |