diff options
| author | Alex Bee <knaerzche@gmail.com> | 2021-05-28 15:05:53 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2021-05-28 19:28:00 +0200 |
| commit | d099fa672cbe8766d9182e0fd04c65058200128a (patch) | |
| tree | b2f75f6c7a9ad48d83bc8a7f4ce8a68967f81a53 /drivers/gpu/drm/rockchip/rockchip_vop_reg.c | |
| parent | 742203cd56d150eb7884eb45abb7d9dbc2bdbf04 (diff) | |
| download | linux-d099fa672cbe8766d9182e0fd04c65058200128a.tar.gz | |
drm: rockchip: add alpha support for RK3036, RK3066, RK3126 and RK3188
With
commit 2aae8ed1f390 ("drm/rockchip: Add per-pixel alpha support for the PX30 VOP")
alpha support was introduced for PX30's VOP.
RK3036, RK3066, RK3126 and RK3188 VOPs support alpha blending in the
same manner.
With the exception of RK3066 all of them support pre-multiplied alpha.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-5-knaerzche@gmail.com
Diffstat (limited to 'drivers/gpu/drm/rockchip/rockchip_vop_reg.c')
| -rw-r--r-- | drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index b7c51933729f..4d18b42f522b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -104,6 +104,9 @@ static const struct vop_win_phy rk3036_win0_data = { .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), + .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), + .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0), + .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), }; static const struct vop_win_phy rk3036_win1_data = { @@ -119,6 +122,9 @@ static const struct vop_win_phy rk3036_win1_data = { .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), + .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), + .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), }; static const struct vop_win_data rk3036_vop_win_data[] = { @@ -185,6 +191,9 @@ static const struct vop_win_phy rk3126_win1_data = { .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), + .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19), + .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29), }; static const struct vop_win_data rk3126_vop_win_data[] = { @@ -364,6 +373,8 @@ static const struct vop_win_phy rk3066_win0_data = { .uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0), .uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16), + .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21), + .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0), }; static const struct vop_win_phy rk3066_win1_data = { @@ -380,6 +391,8 @@ static const struct vop_win_phy rk3066_win1_data = { .uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0), .uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16), + .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22), + .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1), }; static const struct vop_win_phy rk3066_win2_data = { @@ -393,6 +406,8 @@ static const struct vop_win_phy rk3066_win2_data = { .dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0), .yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0), + .alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23), + .alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2), }; static const struct vop_modeset rk3066_modeset = { @@ -478,6 +493,9 @@ static const struct vop_win_phy rk3188_win0_data = { .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0), .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0), + .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 18), + .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 0), + .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), }; static const struct vop_win_phy rk3188_win1_data = { @@ -492,6 +510,9 @@ static const struct vop_win_phy rk3188_win1_data = { .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0), .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0), .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16), + .alpha_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 19), + .alpha_en = VOP_REG(RK3188_ALPHA_CTRL, 0x1, 1), + .alpha_pre_mul = VOP_REG(RK3188_DSP_CTRL0, 0x1, 29), }; static const struct vop_modeset rk3188_modeset = { |