diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-03-26 13:32:21 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-05 23:09:33 +0200 |
| commit | 91eded9b481e61913d98142927b559af33a180a7 (patch) | |
| tree | bcab00eb979434cc358abe43a4f4cf2633d43f06 /drivers/gpu/drm/tegra/dc.c | |
| parent | dbb3f2f751069bc757fbdbe8911a7e784e850b24 (diff) | |
| download | linux-91eded9b481e61913d98142927b559af33a180a7.tar.gz | |
drm/tegra: dc - Compute shift clock divider in output drivers
The shift clock divider is highly dependent on the type of output, so
push computation of it down into the output drivers. The old code used
to work merely by accident.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dc.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 69f48ca78e49..859e424e15e5 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -619,7 +619,7 @@ static int tegra_dc_set_timings(struct tegra_dc *dc, static int tegra_crtc_setup_clk(struct drm_crtc *crtc, struct drm_display_mode *mode) { - unsigned long pclk = mode->clock * 1000, rate; + unsigned long pclk = mode->clock * 1000; struct tegra_dc *dc = to_tegra_dc(crtc); struct tegra_output *output = NULL; struct drm_encoder *encoder; @@ -637,19 +637,16 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc, return -ENODEV; /* - * This assumes that the display controller will divide its parent - * clock by 2 to generate the pixel clock. + * This assumes that the parent clock is pll_d_out0 or pll_d2_out + * respectively, each of which divides the base pll_d by 2. */ - err = tegra_output_setup_clock(output, dc->clk, pclk * 2); + err = tegra_output_setup_clock(output, dc->clk, pclk, &div); if (err < 0) { dev_err(dc->dev, "failed to setup clock: %ld\n", err); return err; } - rate = clk_get_rate(dc->clk); - div = (rate * 2 / pclk) - 2; - - DRM_DEBUG_KMS("rate: %lu, div: %u\n", rate, div); + DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div); value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); |