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authorThierry Reding <treding@nvidia.com>2018-09-21 12:27:42 +0200
committerThierry Reding <treding@nvidia.com>2018-09-26 16:03:51 +0200
commit759d706f7cb4adbec1c222f7550dc8fa2683c089 (patch)
tree2f70d5ae22a0452844bd301f9fe3b83318dca64b /drivers/gpu/drm/tegra
parent47022003f94d1eecf49b9b7a7804814faaea9f08 (diff)
downloadlinux-759d706f7cb4adbec1c222f7550dc8fa2683c089.tar.gz
drm/tegra: dc: Do not register DC without primary plane
Tegra194 contains a fourth display controller that does not own any windows. Therefore, we cannot currently assign a primary plane to it which causes KMS to eventually crash. Do not register the display controller if it owns no windows to work around this. Note that we still have to enable and probe the display controller because for some reason all display controllers need to be powered (and/or clocked) before any registers can be accessed in any of the display controllers. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/dc.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 965088afcfad..7e36ca204cbb 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1988,6 +1988,28 @@ static int tegra_dc_init(struct host1x_client *client)
struct drm_plane *cursor = NULL;
int err;
+ /*
+ * XXX do not register DCs with no window groups because we cannot
+ * assign a primary plane to them, which in turn will cause KMS to
+ * crash.
+ */
+ if (dc->soc->wgrps) {
+ bool has_wgrps = false;
+ unsigned int i;
+
+ for (i = 0; i < dc->soc->num_wgrps; i++) {
+ const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
+
+ if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) {
+ has_wgrps = true;
+ break;
+ }
+ }
+
+ if (!has_wgrps)
+ return 0;
+ }
+
dc->syncpt = host1x_syncpt_request(client, flags);
if (!dc->syncpt)
dev_warn(dc->dev, "failed to allocate syncpoint\n");