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authorDave Olson <dave.olson@qlogic.com>2010-06-17 23:13:44 +0000
committerRoland Dreier <rolandd@cisco.com>2010-07-06 14:13:20 -0700
commitfce24a9d28f8b99fd0eacc14e252ab4fca9527a7 (patch)
tree590717ce8bd0e8a63e072b4bd79b99be69c3b8c8 /drivers/infiniband/hw/qib/qib.h
parent67a3e12b05e055c0415c556a315a3d3eb637e29e (diff)
downloadlinux-fce24a9d28f8b99fd0eacc14e252ab4fca9527a7.tar.gz
IB/qib: Don't mark VL15 bufs as WC to avoid a rare 7322 chip problem
Don't set write combining via PAT on the VL15 buffers to avoid a rare problem with unaligned writes from interrupt-flushed store buffers. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/qib/qib.h')
-rw-r--r--drivers/infiniband/hw/qib/qib.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/qib/qib.h b/drivers/infiniband/hw/qib/qib.h
index 32d9208efcff..3593983df7ba 100644
--- a/drivers/infiniband/hw/qib/qib.h
+++ b/drivers/infiniband/hw/qib/qib.h
@@ -686,6 +686,7 @@ struct qib_devdata {
void __iomem *piobase;
/* mem-mapped pointer to base of user chip regs (if using WC PAT) */
u64 __iomem *userbase;
+ void __iomem *piovl15base; /* base of VL15 buffers, if not WC */
/*
* points to area where PIOavail registers will be DMA'ed.
* Has to be on a page of it's own, because the page will be