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| author | Florian Fainelli <f.fainelli@gmail.com> | 2014-08-22 18:55:45 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-08-23 11:39:09 -0700 |
| commit | b8f9a02924bbeb0c46ca4c19561cbe765b80e264 (patch) | |
| tree | 6990b37910085fec8a0b832f807d9e2c22ff73de /include/linux/brcmphy.h | |
| parent | a9f6309585cbefa4a7f08c9017ca482c3222323a (diff) | |
| download | linux-b8f9a02924bbeb0c46ca4c19561cbe765b80e264.tar.gz | |
net: phy: bcm7xxx: enable EEE at the PHY level
The 28nm Gigabit PHY on BCM7xxx chips comes out of reset with absolutely
no EEE capabilities, such that we would actually return that we do not
support EEE when accessing 3.20 (MDIO_PCS_EEE_ABLE) registers.
Poke through the vendor-specific C45 register to enable EEE globally at
the PHY level, and advertise supported EEE modes.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
| -rw-r--r-- | include/linux/brcmphy.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 722cf26567fa..ee1431d976fa 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -214,5 +214,8 @@ static inline int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, MII_BCM54XX_SHD_DATA(val)); } +#define BRCM_CL45VEN_EEE_CONTROL 0x803d +#define LPI_FEATURE_EN 0x8000 +#define LPI_FEATURE_EN_DIG1000X 0x4000 #endif /* _LINUX_BRCMPHY_H */ |