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* intel_mid: Renamed *mrst* to *intel_mid*Kuppuswamy Sathyanarayanan2013-10-171-310/+0
| | | | | | | | | | | | | | | | | | | | | | Following files contains code that is common to all intel mid soc's. So renamed them as below. mrst/mrst.c -> intel-mid/intel-mid.c mrst/vrtc.c -> intel-mid/intel_mid_vrtc.c mrst/early_printk_mrst.c -> intel-mid/intel_mid_vrtc.c pci/mrst.c -> pci/intel_mid_pci.c Also, renamed the corresponding header files and made changes to the driver files that included these header files. To ensure that there are no functional changes, I have compared the objdump of renamed files before and after rename and found that the only difference is file name change. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: http://lkml.kernel.org/r/1382049336-21316-4-git-send-email-david.a.cohen@linux.intel.com Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* x86/pci/mrst: Cleanup checkpatch.pl warningsValentina Manea2013-07-251-17/+24
| | | | | | | | | | | | | | | This patch fixes warning and errors found by checkpatch.pl: * replace asm/acpi.h, asm/io.h and asm/smp.h with linux/acpi.h, linux/io.h and linux/smp.h respectively * remove explicit initialization to 0 of a static global variable * replace printk(KERN_INFO ...) with pr_info * use tabs instead of spaces for indentation * arrange comments so that they adhere to Documentation/CodingStyle [bhelgaas: capitalize "PCI", "Langwell", "Lincroft" consistently] Signed-off-by: Valentina Manea <valentina.manea.m@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ingo Molnar <mingo@kernel.org>
* Revert "x86/pci/mrst: Use configuration mechanism 1 for 00:00.0, 00:02.0, ↵Bjorn Helgaas2013-05-201-6/+4
| | | | | | | | | | | | 00:03.0" This reverts commit dd72be99d11dbf738d910a38479ce414a51eb21e. Andy Shevchenko <andy.shevchenko@gmail.com> reported that this commit broke Intel Medfield devices. Reference: https://lkml.kernel.org/r/CAHp75Vdf6gFZChS47=grUygHBDWcoOWDYPzw+Zj5bdVCWj85Jw@mail.gmail.com Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* x86/pci/mrst: Use configuration mechanism 1 for 00:00.0, 00:02.0, 00:03.0Bin Gao2013-04-301-4/+6
| | | | | | | | | | | | | | For real PCI devices 00:00.0, 00:02.0 and 00:03.0, there is either no PCI shim, or no guarantee of data correctness of offset 256-4k. So for whatever reason, Linux kernel should not do MMCFG PCI config access to those devices. Instead, always use configuration mechanism 1 for those devices. The 00:00.0, 00:02.0 and 00:03.0 devices are built-in single-function devices and are not PCI-PCI bridges, so this set of devices should be complete. Signed-off-by: Bin Gao <bin.gao@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* X86: drivers: remove __dev* attributes.Greg Kroah-Hartman2013-01-031-3/+3
| | | | | | | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Daniel Drake <dsd@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* PCI: do not call pci_set_power_state with PCI_D3coldHuang Ying2012-06-231-1/+1
| | | | | | | | | | | | | | PCI subsystem has not been ready for D3cold support yet. So PCI_D3cold should not be used as parameter for pci_set_power_state. This patch is needed for upcoming PCI_D3cold support. This patch has no functionality change, because pci_set_power_state will bound the parameter to PCI_D3hot too. CC: Michal Miroslaw <mirq-linux@rere.qmqm.pl> CC: Jesse Barnes <jesse.barnes@intel.com> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* x86/mrst/pci: avoid SoC fixups on non-SoC platformsAlan Cox2012-02-231-1/+11
| | | | | | | | | The PCI fixups get executed based upon whether they are linked in. We need to avoid executing them if we boot a dual SoC/PC type kernel on a PC class system. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86/mrst/pci: v4l/atomisp: treat atomisp as real pci deviceJacob Pan2012-02-231-1/+3
| | | | | | | | | | | ATOMISP on Medfield is a real PCI device which should be handled differently than the fake PCI devices on south complex. PCI type 1 access is used for accessing config space this also has other impact such as PM D3 delay. There shouldn't be any need for reading base address from IUNIT via msg bus. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86/mrst/pci: assign d3_delay to 0 for Langwell devicesJacob Pan2012-02-231-0/+24
| | | | | | | | | | | | Langwell devices are not true pci devices, they are not subject to the 10 ms d3 to d0 delay required by pci spec. This patch assigns d3_delay to 0 for all langwell pci devices. We can also power off devices that are not really used by the OS Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86, pci, mrst: Add extra sanity check in walking the PCI extended cap chainJacob Pan2010-07-161-3/+4
| | | | | | | | | | | | | | | | | The fixed bar capability structure is searched in PCI extended configuration space. We need to make sure there is a valid capability ID to begin with otherwise, the search code may stuck in a infinite loop which results in boot hang. This patch adds additional check for cap ID 0, which is also invalid, and indicates end of chain. End of chain is supposed to have all fields zero, but that doesn't seem to always be the case in the field. Suggested-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> LKML-Reference: <1279306706-27087-1-git-send-email-jacob.jun.pan@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* Merge branch 'x86-mrst-for-linus' of ↵Linus Torvalds2010-05-181-1/+1
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, mrst: add nop functions to x86_init mpparse functions x86, mrst, pci: return 0 for non-present pci bars x86: Avoid check hlt for newer cpus
| * x86, mrst, pci: return 0 for non-present pci barsJacob Pan2010-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moorestown PCI code has special handling of devices with fixed BARs. In case of BAR sizing writes, we need to update the fake PCI MMCFG space with real size decode value. When a BAR is not present, we need to return 0 instead of ~0. ~0 will be treated as device error per bugzilla 12006. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> LKML-Reference: <1273873281-17489-2-git-send-email-jacob.jun.pan@linux.intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
* | x86, mrst: Don't blindly access extended config spaceH. Peter Anvin2010-05-141-0/+4
|/ | | | | | | | | | | | | | | | | | Do not blindly access extended configuration space unless we actively know we're on a Moorestown platform. The fixed-size BAR capability lives in the extended configuration space, and thus is not applicable if the configuration space isn't appropriately sized. This fixes booting certain VMware configurations with CONFIG_MRST=y. Moorestown will add a fake PCI-X 266 capability to advertise the presence of extended configuration space. Reported-and-tested-by: Petr Vandrovec <petr@vandrovec.name> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Acked-by: Jacob Pan <jacob.jun.pan@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> LKML-Reference: <AANLkTiltKUa3TrKR1M51eGw8FLNoQJSLT0k0_K5X3-OJ@mail.gmail.com>
* x86, pci: Add sanity check for PCI fixed bar probingJacob Pan2010-02-241-0/+4
| | | | | | | | | | While probing for the PCI fixed BAR capability in the extended PCI configuration space we need to make sure raw_pci_ext_ops is actually initialized. Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> LKML-Reference: <43F901BD926A4E43B106BF17856F0755A321E8F7@orsmsx508.amr.corp.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* x86/PCI: Moorestown PCI supportJesse Barnes2010-02-231-0/+258
The Moorestown platform only has a few devices that actually support PCI config cycles. The rest of the devices use an in-RAM MCFG space for the purposes of device enumeration and initialization. There are a few uglies in the fake support, like BAR sizes that aren't a power of two, sizing detection, and writes to the real devices, but other than that it's pretty straightforward. Another way to think of this is not really as PCI at all, but just a table in RAM describing which devices are present, their capabilities and their offsets in MMIO space. This could have been done with a special new firmware table on this platform, but given that we do have some real PCI devices too, simply describing things in an MCFG type space was pretty simple. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80D08@orsmsx508.amr.corp.intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>