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path: root/drivers/clk/clk-vt8500.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner2019-06-051-10/+1
* clk: vt8500: Migrate to clk_hw based registration APIsStephen Boyd2016-08-241-10/+12
* clk: vt8500: rework wm8650_find_pll_bits()Roman Volkov2016-06-201-35/+38
* clk: vt8500: fix gcc-4.9 warningsArnd Bergmann2016-06-201-24/+10
* clk: vt8500: don't return possibly uninitialized dataArnd Bergmann2016-02-021-26/+65
* clk: vt8500: fix sign of possible PLL valuesAndrzej Hajda2016-01-291-3/+6
* clk: vt8500: Staticize vtwm_pll_opsSachin Kamat2013-12-191-1/+1
* ARM: vt8500: prepare for arch-wide .init_time callbackSebastian Hesselbarth2013-09-291-10/+0
* clk: vt8500: parse pmc_base from clock driverSebastian Hesselbarth2013-09-291-0/+24
* Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-07-031-4/+71
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| * clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()Tony Prisk2013-05-291-4/+0
| * clk: vt8500: Add support for clocks on the WM8850 SoCsTony Prisk2013-05-291-0/+71
* | clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()Tony Prisk2013-05-291-1/+1
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* Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-04-291-0/+2
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| * clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.Tony Prisk2013-04-141-0/+2
* | clk: vt8500: Fix "fix device clock divisor calculations"Arnd Bergmann2013-03-141-1/+1
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* clk: vt8500: Use common of_clk_init() functionPrashant Gaikwad2013-01-241-12/+5
* clk: vt8500: Add support for WM8750/WM8850 PLL clocksTony Prisk2013-01-151-2/+100
* clk: vt8500: Fix division-by-0 when requested rate=0Tony Prisk2013-01-151-2/+12
* clk: vt8500: Fix device clock divisor calculationsTony Prisk2013-01-151-0/+8
* clk: vt8500: Fix error in PLL calculations on non-exact match.Tony Prisk2013-01-151-3/+3
* CLK: vt8500: Fix SDMMC clk special casesTony Prisk2012-11-091-0/+18
* arm: vt8500: clk: Add Common Clock Framework supportTony Prisk2012-09-211-0/+510
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