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*-. Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...Stephen Boyd2019-11-273-1/+286
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| * | clk: ingenic: Allow drivers to be built with COMPILE_TESTStephen Boyd2019-11-221-1/+1
| * | clk: Ingenic: Add CGU driver for X1000.Zhou Yanjie2019-11-133-0/+285
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* | drivers/clk: convert VL struct to struct_sizeStephen Kitt2019-11-081-2/+1
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* Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-09-224-1/+490
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| * clk: jz4740: Add TCU clockPaul Cercueil2019-08-081-0/+6
| * clk: ingenic: Add driver for the TCU clocksPaul Cercueil2019-08-083-1/+484
* | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil2019-08-124-4/+4
* | clk: ingenic/jz4740: Fix "pll half" divider not read/written properlyPaul Cercueil2019-08-071-1/+8
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-179-128/+192
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| * clk: ingenic: Remove unused functionsPaul Cercueil2019-06-251-73/+0
| * clk: ingenic: Handle setting the Low-Power Mode bitPaul Cercueil2019-06-257-32/+69
| * clk: ingenic: Add missing header in cgu.hPaul Cercueil2019-06-251-0/+1
| * clk: ingenic/jz4725b: Fix "pll half" divider not read/written properlyPaul Cercueil2019-06-071-1/+8
| * clk: ingenic/jz4725b: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| * clk: ingenic/jz4770: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-6/+28
| * clk: ingenic/jz4740: Fix incorrect dividers for main clocksPaul Cercueil2019-06-071-5/+24
| * clk: ingenic: Add support for divider tablesPaul Cercueil2019-06-072-6/+38
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-304-40/+4
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
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* clk: Remove io.h from clk-provider.hStephen Boyd2019-05-154-0/+4
* clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil2019-04-111-0/+6
* clk: ingenic: Remove set but not used variable 'enable'YueHaibing2019-02-261-2/+1
* clk: ingenic: Fix doc of ingenic_cgu_div_infoPaul Cercueil2019-02-221-1/+1
* clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil2019-02-221-5/+5
* clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil2019-02-051-1/+1
* clk: Add Ingenic jz4725b CGU driverPaul Cercueil2018-10-163-0/+236
* clk: ingenic: Add proper Kconfig entriesPaul Cercueil2018-10-162-4/+41
* clk: ingenic: Add missing flag for UDC clockPaul Cercueil2018-07-061-1/+1
* clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil2018-07-061-1/+1
* docs: Fix some broken referencesMauro Carvalho Chehab2018-06-151-1/+1
* clk: ingenic: jz4770: Add 150us delay after enabling VPU clockPaul Cercueil2018-06-011-1/+1
* clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clockPaul Cercueil2018-06-011-2/+2
* clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idlePaul Cercueil2018-06-011-1/+2
* clk: ingenic: jz4770: Change OTG from custom to standard gated clockPaul Cercueil2018-06-011-37/+5
* clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil2018-06-012-0/+5
* clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil2018-06-012-2/+5
* clk: Add Ingenic jz4770 CGU driverPaul Cercueil2018-01-182-0/+484
* clk: ingenic: Add code to enable/disable PLLsPaul Cercueil2018-01-181-15/+74
* clk: ingenic: support PLLs with no bypass bitPaul Cercueil2018-01-182-1/+4
* clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil2018-01-181-0/+2
* clk: ingenic: Use const pointer to clk_ops in structPaul Cercueil2018-01-182-2/+2
* Update MIPS email addressesPaul Burton2017-11-034-4/+4
* clk: ingenic: Allow divider value to be dividedHarvey Hunt2016-05-124-34/+47
* clk: ingenic: Include clk.hStephen Boyd2015-07-201-0/+1
* clk: ingenic: add JZ4780 CGU supportPaul Burton2015-06-212-0/+734
* MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cguPaul Burton2015-06-211-0/+37
* MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cguPaul Burton2015-06-211-0/+22
* MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cguPaul Burton2015-06-211-0/+22
* MIPS,clk: migrate JZ4740 to common clock frameworkPaul Burton2015-06-212-0/+223
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