| Commit message (Expand) | Author | Age | Files | Lines |
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| * | clk: tegra: Add CEC clock | Peter De Schrijver | 2017-03-20 | 1 | -0/+1 |
| * | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker | 2016-06-30 | 1 | -111/+2 |
| * | clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 | Lucas Stach | 2016-04-28 | 1 | -5/+6 |
| * | clk: tegra: Initialize PLL_C to sane rate on Tegra30 | Lucas Stach | 2016-04-28 | 1 | -0/+1 |
| * | clk: tegra: pll: Update PLLM handling | Danny Huang | 2015-11-20 | 1 | -1/+1 |
| * | clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate | Rhyland Klein | 2015-11-20 | 1 | -110/+117 |
| * | clk: tegra: pll: Don't unconditionally set LOCK flags | Rhyland Klein | 2015-11-20 | 1 | -9/+15 |
| * | clk: tegra: Constify pdiv-to-hw mappings | Thierry Reding | 2015-11-20 | 1 | -1/+1 |
| * | clk: tegra: Format tables consistently | Thierry Reding | 2015-11-18 | 1 | -189/+189 |
| * | clk: tegra: Miscellaneous coding style cleanups | Thierry Reding | 2015-11-18 | 1 | -10/+5 |
| * | clk: tegra: Fix 26 MHz oscillator frequency | Thierry Reding | 2015-11-18 | 1 | -1/+1 |
| * | clk: tegra: Modify tegra_audio_clk_init to accept more plls | Rhyland Klein | 2015-10-20 | 1 | -1/+7 |
| * | clk: tegra: Properly include clk.h | Stephen Boyd | 2015-07-20 | 1 | -1/+0 |
| * | clk: tegra: Fix hda2codec_2x clock name for Tegra30 | Marcel Ziswiler | 2015-05-13 | 1 | -1/+1 |
| * | clk: tegra: Model oscillator as clock | Thierry Reding | 2015-04-10 | 1 | -1/+2 |
| * | clk: tegra: Use consistent indentation | Thierry Reding | 2015-04-10 | 1 | -10/+10 |
| * | clk: tegra: Implement memory-controller clock | Thierry Reding | 2014-11-26 | 1 | -1/+6 |
| * | ARM: tegra: Convert PMC to a driver | Thierry Reding | 2014-07-17 | 1 | -1/+1 |
| * | ARM: tegra: Move includes to include/soc/tegra | Thierry Reding | 2014-07-17 | 1 | -1/+4 |
| * | clk: tegra: remove bogus PCIE_XCLK | Stephen Warren | 2013-12-11 | 1 | -7/+0 |
| * | clk: tegra: implement a reset driver | Stephen Warren | 2013-12-11 | 1 | -1/+2 |
| * | clk: tegra: add FUSE clock device | Alexandre Courbot | 2013-11-26 | 1 | -1/+1 |
| * | clk: tegra: Properly setup PWM clock on Tegra30 | Thierry Reding | 2013-11-26 | 1 | -1/+3 |
| * | clk: tegra: Initialize secondary gr3d clock on Tegra30 | Thierry Reding | 2013-11-26 | 1 | -0/+1 |
| * | clk: tegra: move tegra30 to common infra | Peter De Schrijver | 2013-11-26 | 1 | -895/+403 |
| * | clk: tegra: move periph clocks to common file | Peter De Schrijver | 2013-11-26 | 1 | -2/+2 |
| * | clk: tegra: move fields to tegra_clk_pll_params | Peter De Schrijver | 2013-11-26 | 1 | -27/+35 |
| * | clk: tegra: common periph_clk_enb_refcnt and clks | Peter De Schrijver | 2013-11-26 | 1 | -28/+11 |
| * | clk: tegra: simplify periph clock data | Peter De Schrijver | 2013-11-26 | 1 | -201/+116 |
| * | clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks | Peter De Schrijver | 2013-11-26 | 1 | -9/+10 |
| * | clk: tegra30: Don't wait for PLL_U lock bit | Tuomas Tynkkynen | 2013-08-28 | 1 | -1/+1 |
| * | clk: add CLK_SET_RATE_NO_REPARENT flag | James Hogan | 2013-08-19 | 1 | -11/+22 |
| * | clk: tegra30: Fix incorrect placement of __initdata | Sachin Kamat | 2013-08-08 | 1 | -1/+1 |
| * | Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux | Linus Torvalds | 2013-07-03 | 1 | -3/+22 |
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| | * | clk: tegra: override bits for Tegra30 PLLM | Peter De Schrijver | 2013-06-11 | 1 | -0/+18 |
| | * | clk: tegra: Use common of_clk_init function | Prashant Gaikwad | 2013-05-31 | 1 | -1/+2 |
| | * | clk: tegra: fix clk_out parents list | Prashant Gaikwad | 2013-05-31 | 1 | -2/+2 |
| * | | ARM: tegra30: clocks: Fix pciex clock registration | Jay Agarwal | 2013-06-16 | 1 | -5/+6 |
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| * | Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi... | Linus Torvalds | 2013-05-04 | 1 | -131/+145 |
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| | * | clk: tegra: Add flags to tegra_clk_periph() | Peter De Schrijver | 2013-04-04 | 1 | -1/+1 |
| | * | clk: tegra: move from a lock bit idx to a lock mask | Peter De Schrijver | 2013-04-04 | 1 | -11/+11 |
| | * | clk: tegra: Add PLL post divider table | Peter De Schrijver | 2013-04-04 | 1 | -0/+7 |
| | * | clk: tegra: Refactor PLL programming code | Peter De Schrijver | 2013-04-04 | 1 | -117/+117 |
| | * | clk: tegra: defer application of init table | Stephen Warren | 2013-04-04 | 1 | -1/+6 |
| | * | clk: tegra: Fix cdev1 and cdev2 IDs | Prashant Gaikwad | 2013-04-04 | 1 | -1/+1 |
| | * | clk: tegra: Make gr2d and gr3d clocks children of pll_c | Thierry Reding | 2013-04-04 | 1 | -0/+2 |
| * | | Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linu... | Arnd Bergmann | 2013-04-09 | 1 | -2/+1 |
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| | * | ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h> | Stephen Warren | 2013-03-29 | 1 | -2/+1 |
| * | | clk: Tegra: Remove duplicate smp_twd clock | Prashant Gaikwad | 2013-03-04 | 1 | -1/+0 |
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| * | clk: tegra: initialise parent of uart clocks | Laxman Dewangan | 2013-02-13 | 1 | -1/+5 |
