summaryrefslogtreecommitdiff
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
* treewide: replace '---help---' in Kconfig files with 'help'Masahiro Yamada2020-06-146-60/+60
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-06-10130-612/+13263
|\
| * clk: mediatek: Remove ifr{0,1}_cfg_regs structuresStephen Boyd2020-06-091-30/+0
| * clk: baikal-t1: remove redundant assignment to variable 'divider'Colin Ian King2020-06-091-1/+1
| * clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"Colin Ian King2020-06-091-1/+1
| *-----. Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into cl...Stephen Boyd2020-06-0122-32/+3644
| |\ \ \ \
| | | | | * clk: Add Baikal-T1 CCU Dividers driverSerge Semin2020-05-305-0/+1210
| | | | | * clk: Add Baikal-T1 CCU PLLs driverSerge Semin2020-05-307-0/+860
| | | | * | clk: mediatek: assign the initial value to clk_init_data of mtk_muxWeiyi Lu2020-05-281-1/+1
| | | | * | clk: mediatek: Add MT6765 clock supportOwen Chen2020-05-289-0/+1523
| | | | |/
| | | * | CLK: HSDK: CGU: add support for 148.5MHz clockEugeniy Paltsev2020-05-281-0/+1
| | | * | CLK: HSDK: CGU: support PLL bypassingEugeniy Paltsev2020-05-281-27/+34
| | | * | CLK: HSDK: CGU: check if PLL is bypassed firstEugeniy Paltsev2020-05-281-4/+4
| | | |/
| | * | clk: vc5: Add support for IDT VersaClock 5P49V6965Adam Ford2020-05-301-0/+11
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-sil...Stephen Boyd2020-06-0135-82/+7246
| |\ \ \ \ \ \
| | | | | | * | clk: clk-si5341: Add support for the Si5345 seriesMike Looijmans2020-05-281-5/+64
| | | | | | |/
| | | | | * | clk: qcom: Add missing msm8998 ufs_unipro_core_clk_srcJeffrey Hugo2020-05-281-0/+27
| | | | | * | clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock ControllerBryan O'Donoghue2020-05-263-0/+3997
| | | | | * | clk: qcom: gcc: Add support for Secure control source clockTaniya Das2020-05-261-0/+21
| | | | | * | clk: qcom: gcc: Add support for a new frequency for SC7180Taniya Das2020-05-261-36/+37
| | | | | * | clk: qcom: gcc: Add missing UFS clocks for SM8150Vinod Koul2020-05-141-0/+84
| | | | | * | clk: qcom: gcc: Add GPU and NPU clocks for SM8150Vinod Koul2020-05-141-0/+64
| | | | | * | clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson2020-05-141-0/+2
| | | | | * | clk: qcom: gdsc: Handle GDSC regulator suppliesBjorn Andersson2020-05-142-0/+27
| | | | | * | clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue2020-04-211-4/+4
| | | | | |/
| | | | * | clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-281-1/+1
| | | | * | clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-281-6/+111
| | | | * | clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-283-0/+459
| | | | * | clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-287-4/+41
| | | | * | clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
| | | | |/
| | | * | clk: intel: remove redundant initialization of variable rate64Colin Ian King2020-05-281-1/+1
| | | * | clk: intel: Add CGU clock driver for a new SoCRahul Tanwar2020-05-267-0/+1612
| | | |/
| | * | clk: mmp2: Add audio clock controller driverLubomir Rintel2020-05-273-0/+450
| | * | clk: mmp2: Add support for power islandsLubomir Rintel2020-05-274-1/+168
| | * | clk: mmp2: Add the audio clockLubomir Rintel2020-05-271-0/+4
| | * | clk: mmp2: Add the I2S clocksLubomir Rintel2020-05-271-0/+46
| | * | clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()Lubomir Rintel2020-05-271-2/+2
| | * | clk: mmp2: Move thermal register defines up a bitLubomir Rintel2020-05-271-4/+4
| | * | clk: mmp: frac: Allow setting bits other than the numerator/denominatorLubomir Rintel2020-05-272-0/+4
| | * | clk: mmp: frac: Do not lose last 4 digits of precisionLubomir Rintel2020-05-271-8/+16
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2...Stephen Boyd2020-06-0110-66/+136
| |\ \ \ \ \ \
| | | | | | * | clk: ast2600: Fix AHB clock divider for A1Eddie James2020-05-271-6/+25
| | | | | | |/
| | | | | * | clk: clk-flexgen: fix clock-critical handlingAlain Volmat2020-05-271-0/+1
| | | | | |/
| | | | * | clk: bcm2835: Constify struct debugfs_reg32Rikard Falkeborn2020-05-271-3/+3
| | | | * | clk: bcm2835: Remove casting to bcm2835_clk_registerNathan Chancellor2020-05-261-31/+37
| | | | * | clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor2020-05-261-5/+5
| | | | |/
| | | * | clk: versatile: remove redundant assignment to pointer clkColin Ian King2020-05-261-1/+1
| | | * | clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET2020-05-051-1/+1
| | | * | clk: Remove unused inline function clk_debug_reparentYueHaibing2020-05-051-4/+0
| | | |/
| | * | clk: sprd: add mipi_csi_xx gate clocksChunyan Zhang2020-05-261-0/+32
View Lorry Controller Status