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path: root/drivers/gpu/drm/i915/display/intel_bw.h
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* drm/i915: Add "maximum pipe read bandwidth" checksVille Syrjälä2022-03-211-0/+1
* drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä2022-03-211-4/+6
* drm/i915: Nuke intel_bw_calc_min_cdclk()Ville Syrjälä2022-03-211-1/+0
* drm/i915: Widen the QGV point maskVille Syrjälä2022-02-161-4/+4
* drm/i915: Fix includes and local vars orderStanislav Lisovskiy2020-05-221-1/+1
* drm/i915: Adjust CDCLK accordingly to our DBuf bw needsStanislav Lisovskiy2020-05-211-0/+10
* drm/i915: Restrict qgv points which don't have enough bandwidth.Stanislav Lisovskiy2020-05-141-0/+9
* drm/i915: Track active_pipes in bw_stateStanislav Lisovskiy2020-05-041-0/+3
* drm/i915: Use bw state for per crtc SAGV evaluationStanislav Lisovskiy2020-05-041-0/+6
* drm/i915: Add intel_atomic_get_bw_*_state helpersStanislav Lisovskiy2020-04-171-0/+9
* drm/i915: Convert bandwidth state to global stateVille Syrjälä2020-01-311-2/+2
* drm/i915/display: cleanup intel_bw_state on i915 module removalPankaj Bharadiya2019-12-241-0/+1
* drm/i915/bw: make intel_atomic_get_bw_state() staticJani Nikula2019-08-071-15/+0
* drm/i915: move modesetting core code under display/Jani Nikula2019-06-171-0/+47
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