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// SPDX-License-Identifier: BSD-3-Clause
/*
* SDX55 SoC device tree source
*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2020, Linaro Ltd.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
interrupt-parent = <&intc>;
memory {
device_type = "memory";
reg = <0 0>;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdx55";
reg = <0x100000 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
blsp1_uart3: serial@831000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x00831000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
clocks = <&gcc 30>,
<&gcc 9>;
clock-names = "core", "iface";
status = "disabled";
};
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx55-pdc", "qcom,pdc";
reg = <0x0b210000 0x30000>;
qcom,pdc-ranges = <0 179 52>;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
interrupt-controller;
};
intc: interrupt-controller@17800000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
reg = <0x17800000 0x1000>,
<0x17802000 0x1000>;
};
timer@17820000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17820000 0x1000>;
clock-frequency = <19200000>;
frame@17821000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>,
<GIC_SPI 6 0x4>;
reg = <0x17821000 0x1000>,
<0x17822000 0x1000>;
};
frame@17823000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>;
reg = <0x17823000 0x1000>;
status = "disabled";
};
frame@17824000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>;
reg = <0x17824000 0x1000>;
status = "disabled";
};
frame@17825000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>;
reg = <0x17825000 0x1000>;
status = "disabled";
};
frame@17826000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>;
reg = <0x17826000 0x1000>;
status = "disabled";
};
frame@17827000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>;
reg = <0x17827000 0x1000>;
status = "disabled";
};
frame@17828000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>;
reg = <0x17828000 0x1000>;
status = "disabled";
};
frame@17829000 {
frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>;
reg = <0x17829000 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@17840000 {
compatible = "qcom,rpmh-rsc";
reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
reg-names = "drv-0", "drv-1";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <1>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sdx55-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};
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