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author | sstwcw <f0gukp2nk@protonmail.com> | 2023-04-30 22:26:41 +0000 |
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committer | sstwcw <f0gukp2nk@protonmail.com> | 2023-04-30 22:26:53 +0000 |
commit | 4134f836103ebc70cc23a80c7a966d1d5f3a6353 (patch) | |
tree | 5b05bf2721787a6ec5b83fd7c2abd9321e475d9a /clang/unittests | |
parent | 82a90caa88fdc632ea2c8495ea3237065272a3a0 (diff) | |
download | llvm-4134f836103ebc70cc23a80c7a966d1d5f3a6353.tar.gz |
[clang-format] Recognize Verilog type dimension in module header
We had the function `verilogGroupDecl` for that. However, the type
name would be incorrectly annotated in `isStartOfName` when it was not
a C++ keyword and followed another identifier.
Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay
Differential Revision: https://reviews.llvm.org/D149352
Diffstat (limited to 'clang/unittests')
-rw-r--r-- | clang/unittests/Format/FormatTestVerilog.cpp | 6 | ||||
-rw-r--r-- | clang/unittests/Format/TokenAnnotatorTest.cpp | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp index ff6a1cdc57fe..a7ba3c57c55b 100644 --- a/clang/unittests/Format/FormatTestVerilog.cpp +++ b/clang/unittests/Format/FormatTestVerilog.cpp @@ -359,6 +359,12 @@ TEST_F(FormatTestVerilog, Headers) { " input var shortreal in2,\n" " output tagged_st out);\n" "endmodule"); + // There should be a space following the type but not the variable name. + verifyFormat("module test\n" + " (input wire [7 : 0] a,\n" + " input wire b[7 : 0],\n" + " input wire [7 : 0] c[7 : 0]);\n" + "endmodule"); // Ports should be grouped by types. verifyFormat("module test\n" " (input [7 : 0] a,\n" diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 62a83596600e..908a81d09f0e 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1615,6 +1615,13 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) { Tokens = Annotate("extern function [1 : 0] x;"); ASSERT_EQ(Tokens.size(), 10u) << Tokens; EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon); + Tokens = Annotate("module test\n" + " (input wire [7 : 0] a[7 : 0]);\n" + "endmodule"); + ASSERT_EQ(Tokens.size(), 20u) << Tokens; + EXPECT_TOKEN(Tokens[4], tok::identifier, TT_VerilogDimensionedTypeName); + EXPECT_TOKEN(Tokens[7], tok::colon, TT_BitFieldColon); + EXPECT_TOKEN(Tokens[13], tok::colon, TT_BitFieldColon); // Test case labels and ternary operators. Tokens = Annotate("case (x)\n" " x:\n" |