[clang-format] Recognize Verilog edge identifiers

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma.  The events can be
separated with either a comma or the `or` keyword, and a line break
would not be inserted if the `or` keyword was used.  We changed the
behavior of the comma to match the `or` keyword.

Before:
```
always @(posedge x,
         posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

After:
```
always @(posedge x, posedge y)
  x <= x;
always @(posedge x or posedge y)
  x <= x;
```

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149561

2 files changed, 17 insertions, 0 deletions

diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index a7ba3c57c55b..a95e572b62fd 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -1157,6 +1157,14 @@ TEST_F(FormatTestVerilog, StructuredProcedure) {
                "  x <= x;");
   verifyFormat("always @(posedge x)\n"
                "  x <= x;");
+  verifyFormat("always @(posedge x or posedge y)\n"
+               "  x <= x;");
+  verifyFormat("always @(posedge x, posedge y)\n"
+               "  x <= x;");
+  verifyFormat("always @(negedge x, negedge y)\n"
+               "  x <= x;");
+  verifyFormat("always @(edge x, edge y)\n"
+               "  x <= x;");
   verifyFormat("always\n"
                "  x <= x;");
   verifyFormat("always @*\n"
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 908a81d09f0e..93f7f710d32c 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -1684,6 +1684,15 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) {
   Tokens = Annotate("case (x) endcase;");
   ASSERT_EQ(Tokens.size(), 7u) << Tokens;
   EXPECT_TOKEN(Tokens[1], tok::l_paren, TT_ConditionLParen);
+
+  // Sensitivity list. The TT_Unknown type is clearly not binding for the
+  // future, please adapt if those tokens get annotated.  This test is only here
+  // to prevent the comma from being annotated as TT_VerilogInstancePortComma.
+  Tokens = Annotate("always @(posedge x, posedge y);");
+  ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+  EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_Unknown);
+  EXPECT_TOKEN(Tokens[5], tok::comma, TT_Unknown);
+  EXPECT_TOKEN(Tokens[8], tok::r_paren, TT_Unknown);
 }
 
 TEST_F(TokenAnnotatorTest, UnderstandConstructors) {