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| author | 4vtomat <brandon.wu@sifive.com> | 2023-03-18 05:15:24 -0700 |
|---|---|---|
| committer | 4vtomat <brandon.wu@sifive.com> | 2023-05-02 05:51:51 -0700 |
| commit | fa43608d1649553814a179cd76d67ea7bdc068d3 (patch) | |
| tree | 76b9379105c2e42e4f68e7012af9fae5de42abd6 /clang/utils | |
| parent | 8efc7de0e639fb3753d0751859e2f62d8de97f70 (diff) | |
| download | llvm-fa43608d1649553814a179cd76d67ea7bdc068d3.tar.gz | |
[RISCV][RISCV][clang] Split out SiFive Vector C intrinsics from riscv_vector.td
Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.
Depends on D148223 and D148680
Differential Revision: https://reviews.llvm.org/D148308
Diffstat (limited to 'clang/utils')
| -rw-r--r-- | clang/utils/TableGen/TableGen.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index a67e1d1af5d7..2fc6639d832f 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -91,6 +91,9 @@ enum ActionType { GenRISCVVectorBuiltins, GenRISCVVectorBuiltinCG, GenRISCVVectorBuiltinSema, + GenRISCVSiFiveVectorBuiltins, + GenRISCVSiFiveVectorBuiltinCG, + GenRISCVSiFiveVectorBuiltinSema, GenAttrDocs, GenDiagDocs, GenOptDocs, @@ -251,6 +254,12 @@ cl::opt<ActionType> Action( "Generate riscv_vector_builtin_cg.inc for clang"), clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema", "Generate riscv_vector_builtin_sema.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltins, "gen-riscv-sifive-vector-builtins", + "Generate riscv_sifive_vector_builtins.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltinCG, "gen-riscv-sifive-vector-builtin-codegen", + "Generate riscv_sifive_vector_builtin_cg.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltinSema, "gen-riscv-sifive-vector-builtin-sema", + "Generate riscv_sifive_vector_builtin_sema.inc for clang"), clEnumValN(GenAttrDocs, "gen-attr-docs", "Generate attribute documentation"), clEnumValN(GenDiagDocs, "gen-diag-docs", @@ -472,6 +481,15 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenRISCVVectorBuiltinSema: EmitRVVBuiltinSema(Records, OS); break; + case GenRISCVSiFiveVectorBuiltins: + EmitRVVBuiltins(Records, OS); + break; + case GenRISCVSiFiveVectorBuiltinCG: + EmitRVVBuiltinCG(Records, OS); + break; + case GenRISCVSiFiveVectorBuiltinSema: + EmitRVVBuiltinSema(Records, OS); + break; case GenAttrDocs: EmitClangAttrDocs(Records, OS); break; |