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| author | Craig Topper <craig.topper@sifive.com> | 2023-03-27 09:15:53 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-03-27 09:50:17 -0700 |
| commit | 29463612d21b7d630476fcecdc8301ddf5634bf7 (patch) | |
| tree | d48e10ca89b0b3dfc9c316caf4ec178509e3d945 /lld/ELF | |
| parent | edc1c8d290efb998a99a08de025d1c63f834c605 (diff) | |
| download | llvm-29463612d21b7d630476fcecdc8301ddf5634bf7.tar.gz | |
[RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.
More patches will follow.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146449
Diffstat (limited to 'lld/ELF')
| -rw-r--r-- | lld/ELF/InputSection.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 2db644c190a2..3057cedb4bdc 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -724,7 +724,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, p = p & 0xfffffffc; if (sym.isUndefined()) { // On ARM and AArch64 a branch to an undefined weak resolves to the next - // instruction, otherwise the place. On RISCV, resolve an undefined weak + // instruction, otherwise the place. On RISC-V, resolve an undefined weak // to the same instruction to cause an infinite loop (making the user // aware of the issue) while ensuring no overflow. // Note: if the symbol is hidden, its binding has been converted to local, |