[RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

New versions I2.1, F2.2, D2.2 A2.1

Make F and Zfinx imply Zicsr.
Make G imply Zifencei.

This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly.

See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147179

2 files changed, 19 insertions, 19 deletions

diff --git a/lld/test/ELF/lto/riscv-attributes.ll b/lld/test/ELF/lto/riscv-attributes.ll
index eb99397bbda8..802eac0bc510 100644
--- a/lld/test/ELF/lto/riscv-attributes.ll
+++ b/lld/test/ELF/lto/riscv-attributes.ll
@@ -10,10 +10,10 @@
 ; CHECK:      BuildAttributes {
 ; CHECK-NEXT:   FormatVersion: 0x41
 ; CHECK-NEXT:   Section 1 {
-; CHECK-NEXT:     SectionLength: 61
+; CHECK-NEXT:     SectionLength: 70
 ; CHECK-NEXT:     Vendor: riscv
 ; CHECK-NEXT:     Tag: Tag_File (0x1)
-; CHECK-NEXT:     Size: 51
+; CHECK-NEXT:     Size: 60
 ; CHECK-NEXT:     FileAttributes {
 ; CHECK-NEXT:       Attribute {
 ; CHECK-NEXT:         Tag: 4
@@ -30,7 +30,7 @@
 ; CHECK-NEXT:       Attribute {
 ; CHECK-NEXT:         Tag: 5
 ; CHECK-NEXT:         TagName: arch
-; CHECK-NEXT:         Value: rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zbb1p0
+; CHECK-NEXT:         Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}}
 ; CHECK-NEXT:       }
 ; CHECK-NEXT:     }
 ; CHECK-NEXT:   }
@@ -38,10 +38,10 @@
 
 ;--- 1.s
 .attribute 4, 16
-.attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
 ;--- 2.s
 .attribute 4, 16
-.attribute 5, "rv32i2p0_m2p0_f2p0_d2p0_zbb1p0"
+.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0"
 .attribute 6, 1
 
 ;--- a.ll
diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s
index f95924be283d..147312c70a1a 100644
--- a/lld/test/ELF/riscv-attributes.s
+++ b/lld/test/ELF/riscv-attributes.s
@@ -66,10 +66,10 @@
 # CHECK:      BuildAttributes {
 # CHECK-NEXT:   FormatVersion: 0x41
 # CHECK-NEXT:   Section 1 {
-# CHECK-NEXT:     SectionLength: 52
+# CHECK-NEXT:     SectionLength: 61
 # CHECK-NEXT:     Vendor: riscv
 # CHECK-NEXT:     Tag: Tag_File (0x1)
-# CHECK-NEXT:     Size: 42
+# CHECK-NEXT:     Size: 51
 # CHECK-NEXT:     FileAttributes {
 # CHECK-NEXT:       Attribute {
 # CHECK-NEXT:         Tag: 4
@@ -80,7 +80,7 @@
 # CHECK-NEXT:       Attribute {
 # CHECK-NEXT:         Tag: 5
 # CHECK-NEXT:         TagName: arch
-# CHECK-NEXT:         Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
+# CHECK-NEXT:         Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}}
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   }
@@ -89,10 +89,10 @@
 # CHECK2:      BuildAttributes {
 # CHECK2-NEXT:   FormatVersion: 0x41
 # CHECK2-NEXT:   Section 1 {
-# CHECK2-NEXT:     SectionLength: 95
+# CHECK2-NEXT:     SectionLength: 104
 # CHECK2-NEXT:     Vendor: riscv
 # CHECK2-NEXT:     Tag: Tag_File (0x1)
-# CHECK2-NEXT:     Size: 85
+# CHECK2-NEXT:     Size: 94
 # CHECK2-NEXT:     FileAttributes {
 # CHECK2-NEXT:       Attribute {
 # CHECK2-NEXT:         Tag: 4
@@ -119,7 +119,7 @@
 # CHECK2-NEXT:       Attribute {
 # CHECK2-NEXT:         Tag: 5
 # CHECK2-NEXT:         TagName: arch
-# CHECK2-NEXT:         Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0
+# CHECK2-NEXT:         Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
 # CHECK2-NEXT:       }
 # CHECK2-NEXT:     }
 # CHECK2-NEXT:   }
@@ -136,7 +136,7 @@
 # CHECK3-NEXT:       Attribute {
 # CHECK3-NEXT:         Tag: 5
 # CHECK3-NEXT:         TagName: arch
-# CHECK3-NEXT:         Value: rv64i99p0
+# CHECK3-NEXT:         Value: rv64i99p0{{$}}
 # CHECK3-NEXT:       }
 # CHECK3-NEXT:     }
 # CHECK3-NEXT:   }
@@ -144,18 +144,18 @@
 
 #--- a.s
 .attribute stack_align, 16
-.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
 .attribute unaligned_access, 0
 
 #--- b.s
 .attribute stack_align, 16
-.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
+.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
 .attribute priv_spec, 2
 .attribute priv_spec_minor, 2
 
 #--- c.s
 .attribute stack_align, 16
-.attribute arch, "rv64i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+.attribute arch, "rv64i2p1_f2p2_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 .attribute unaligned_access, 1
 .attribute priv_spec, 2
 .attribute priv_spec_minor, 2
@@ -172,7 +172,7 @@
 # UNRECOGNIZED_EXT1-NEXT:       Attribute {
 # UNRECOGNIZED_EXT1-NEXT:         Tag: 5
 # UNRECOGNIZED_EXT1-NEXT:         TagName: arch
-# UNRECOGNIZED_EXT1-NEXT:         Value: rv64i2p0_y2p0
+# UNRECOGNIZED_EXT1-NEXT:         Value: rv64i2p1_y2p0{{$}}
 # UNRECOGNIZED_EXT1-NEXT:       }
 # UNRECOGNIZED_EXT1-NEXT:     }
 # UNRECOGNIZED_EXT1-NEXT:   }
@@ -185,7 +185,7 @@
 .byte 1  # Tag_File
 .long .Lend-.Lbegin
 .byte 5  # Tag_RISCV_arch
-.asciz "rv64i2p0_y2p0"
+.asciz "rv64i2p1_y2p0"
 .Lend:
 
 #--- unrecognized_ext2.s
@@ -200,7 +200,7 @@
 # UNRECOGNIZED_EXT2-NEXT:       Attribute {
 # UNRECOGNIZED_EXT2-NEXT:         Tag: 5
 # UNRECOGNIZED_EXT2-NEXT:         TagName: arch
-# UNRECOGNIZED_EXT2-NEXT:         Value: rv64i2p0_zmadeup1p0
+# UNRECOGNIZED_EXT2-NEXT:         Value: rv64i2p1_zmadeup1p0{{$}}
 # UNRECOGNIZED_EXT2-NEXT:       }
 # UNRECOGNIZED_EXT2-NEXT:     }
 # UNRECOGNIZED_EXT2-NEXT:   }
@@ -213,7 +213,7 @@
 .byte 1  # Tag_File
 .long .Lend-.Lbegin
 .byte 5  # Tag_RISCV_arch
-.asciz "rv64i2p0_zmadeup1p0"
+.asciz "rv64i2p1_zmadeup1p0"
 .Lend:
 
 #--- unrecognized_version.s