[mlir][arith] Rename addui_carry to addui_extended

The goal is to make the naming of the future `_extended` ops more
consistent. With unsigned addition, the carry value/flag and overflow
bit are the same, but this is not true when it comes to signed addition.

Also rename the second result from `carry` to `overflow`.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D139569

1 files changed, 5 insertions, 4 deletions

diff --git a/mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp b/mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
index 28134cf11932..f10fefba87ee 100644
--- a/mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
+++ b/mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
@@ -276,11 +276,12 @@ struct ConvertAddI final : OpConversionPattern<arith::AddIOp> {
     auto [rhsElem0, rhsElem1] =
         extractLastDimHalves(rewriter, loc, adaptor.getRhs());
 
-    auto lowSum = rewriter.create<arith::AddUICarryOp>(loc, lhsElem0, rhsElem0);
-    Value carryVal =
-        rewriter.create<arith::ExtUIOp>(loc, newElemTy, lowSum.getCarry());
+    auto lowSum =
+        rewriter.create<arith::AddUIExtendedOp>(loc, lhsElem0, rhsElem0);
+    Value overflowVal =
+        rewriter.create<arith::ExtUIOp>(loc, newElemTy, lowSum.getOverflow());
 
-    Value high0 = rewriter.create<arith::AddIOp>(loc, carryVal, lhsElem1);
+    Value high0 = rewriter.create<arith::AddIOp>(loc, overflowVal, lhsElem1);
     Value high = rewriter.create<arith::AddIOp>(loc, high0, rhsElem1);
 
     Value resultVec =