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authorJeremy Furtek <jfurtek@nvidia.com>2022-10-26 11:07:20 -0700
committerSlava Zakharin <szakharin@nvidia.com>2022-10-26 11:56:16 -0700
commitb56e65d31825fe4a1ae02fdcbad58bb7993d63a7 (patch)
tree9c5da7d952fc34b6716f9f19b8347f1a8906944c /mlir/lib/Dialect/X86Vector
parentf6eb089734ddbd7f9b9935a122ff4ad658f06360 (diff)
downloadllvm-b56e65d31825fe4a1ae02fdcbad58bb7993d63a7.tar.gz
[mlir][arith] Initial support for fastmath flag attributes in the Arithmetic dialect (v2)
This diff adds initial (partial) support for "fastmath" attributes for floating point operations in the arithmetic dialect. The "fastmath" attributes are implemented using a default-valued bit enum. The defined flags currently mirror the fastmath flags in the LLVM dialect (and in LLVM itself). Extending the set of flags (if necessary) is left as a future task. In this diff: - Definition of FastMathAttr as a custom attribute in the Arithmetic dialect that inherits from the EnumAttr class. - Definition of ArithFastMathInterface, which is an interface that is implemented by operations that have an arith::fastmath attribute. - Declaration of a default-valued fastmath attribute for unary and (some) binary floating point operations in the Arithmetic dialect. - Conversion code to lower arithmetic fastmath flags to LLVM fastmath flags NOT in this diff (but planned or currently in progress): - Documentation of flag meanings - Addition of FastMathAttr attributes to other dialects that might lower to the Arithmetic dialect (e.g. Math and Complex) - Folding/rewrite implementations that are enabled by fastmath flags - Specification of fastmath values from Python bindings (pending other in- progress diffs) Reviewed By: mehdi_amini, vzakhari Differential Revision: https://reviews.llvm.org/D126305
Diffstat (limited to 'mlir/lib/Dialect/X86Vector')
-rw-r--r--mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp b/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
index ea86819faf1c..1aee27560ea3 100644
--- a/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
+++ b/mlir/lib/Dialect/X86Vector/Transforms/LegalizeForLLVMExport.cpp
@@ -51,13 +51,13 @@ struct LowerToIntrinsic : public OpConversionPattern<OpTy> {
Type elementType = getSrcVectorElementType<OpTy>(op);
unsigned bitwidth = elementType.getIntOrFloatBitWidth();
if (bitwidth == 32)
- return LLVM::detail::oneToOneRewrite(op, Intr32OpTy::getOperationName(),
- adaptor.getOperands(),
- getTypeConverter(), rewriter);
+ return LLVM::detail::oneToOneRewrite(
+ op, Intr32OpTy::getOperationName(), adaptor.getOperands(),
+ op->getAttrs(), getTypeConverter(), rewriter);
if (bitwidth == 64)
- return LLVM::detail::oneToOneRewrite(op, Intr64OpTy::getOperationName(),
- adaptor.getOperands(),
- getTypeConverter(), rewriter);
+ return LLVM::detail::oneToOneRewrite(
+ op, Intr64OpTy::getOperationName(), adaptor.getOperands(),
+ op->getAttrs(), getTypeConverter(), rewriter);
return rewriter.notifyMatchFailure(
op, "expected 'src' to be either f32 or f64");
}