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| author | Benjamin Chetioui <bchetioui@google.com> | 2023-05-09 10:21:07 +0000 |
|---|---|---|
| committer | Benjamin Chetioui <bchetioui@google.com> | 2023-05-09 10:21:07 +0000 |
| commit | 7e9f0f1fa8ef1dd5b935d7679cad311db6026959 (patch) | |
| tree | af4d4bda6f88ffb45bb3942e963510bf61d54f15 /utils | |
| parent | 629170fe452f4849c89fc289d6e2cf5f08534342 (diff) | |
| download | llvm-7e9f0f1fa8ef1dd5b935d7679cad311db6026959.tar.gz | |
[bazel] Port BUILD rules for 92cc30aca78703174e89880aca85e5a5ff41cc98.
Diffstat (limited to 'utils')
| -rw-r--r-- | utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index eef474ee0af0..73f79d3353ec 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -1018,8 +1018,8 @@ td_library( ) td_library( - name = "Mem2RegInterfacesTdFiles", - srcs = ["include/mlir/Interfaces/Mem2RegInterfaces.td"], + name = "MemorySlotInterfacesTdFiles", + srcs = ["include/mlir/Interfaces/MemorySlotInterfaces.td"], includes = ["include"], deps = [":OpBaseTdFiles"], ) @@ -3203,13 +3203,13 @@ cc_library( ) cc_library( - name = "Mem2RegInterfaces", - srcs = ["lib/Interfaces/Mem2RegInterfaces.cpp"], - hdrs = ["include/mlir/Interfaces/Mem2RegInterfaces.h"], + name = "MemorySlotInterfaces", + srcs = ["lib/Interfaces/MemorySlotInterfaces.cpp"], + hdrs = ["include/mlir/Interfaces/MemorySlotInterfaces.h"], includes = ["include"], deps = [ ":IR", - ":Mem2RegInterfacesIncGen", + ":MemorySlotInterfacesIncGen", "//llvm:Support", ], ) @@ -4032,8 +4032,8 @@ cc_library( ":LLVMIntrinsicOpsIncGen", ":LLVMOpsIncGen", ":LLVMTypesIncGen", - ":Mem2RegInterfaces", - ":Mem2RegInterfacesIncGen", + ":MemorySlotInterfaces", + ":MemorySlotInterfacesIncGen", ":SideEffectInterfaces", ":Support", "//llvm:AsmParser", @@ -4435,7 +4435,7 @@ td_library( ":DataLayoutInterfacesTdFiles", ":FunctionInterfacesTdFiles", ":InferTypeOpInterfaceTdFiles", - ":Mem2RegInterfacesTdFiles", + ":MemorySlotInterfacesTdFiles", ":OpBaseTdFiles", ":SideEffectInterfacesTdFiles", ], @@ -5975,7 +5975,7 @@ cc_library( ":ControlFlowInterfaces", ":IR", ":LoopLikeInterface", - ":Mem2RegInterfaces", + ":MemorySlotInterfaces", ":Rewrite", ":SideEffectInterfaces", ":Support", @@ -6132,21 +6132,21 @@ gentbl_cc_library( ) gentbl_cc_library( - name = "Mem2RegInterfacesIncGen", + name = "MemorySlotInterfacesIncGen", strip_include_prefix = "include", tbl_outs = [ ( ["-gen-op-interface-decls"], - "include/mlir/Interfaces/Mem2RegInterfaces.h.inc", + "include/mlir/Interfaces/MemorySlotOpInterfaces.h.inc", ), ( ["-gen-op-interface-defs"], - "include/mlir/Interfaces/Mem2RegInterfaces.cpp.inc", + "include/mlir/Interfaces/MemorySlotOpInterfaces.cpp.inc", ), ], tblgen = ":mlir-tblgen", - td_file = "include/mlir/Interfaces/Mem2RegInterfaces.td", - deps = [":Mem2RegInterfacesTdFiles"], + td_file = "include/mlir/Interfaces/MemorySlotInterfaces.td", + deps = [":MemorySlotInterfacesTdFiles"], ) gentbl_cc_library( @@ -6304,7 +6304,7 @@ cc_library( ":ControlFlowInterfaces", ":IR", ":LoopLikeInterface", - ":Mem2RegInterfaces", + ":MemorySlotInterfaces", ":Pass", ":Rewrite", ":RuntimeVerifiableOpInterface", @@ -10502,7 +10502,7 @@ td_library( ], includes = ["include"], deps = [ - ":Mem2RegInterfacesTdFiles", + ":MemorySlotInterfacesTdFiles", ":ArithOpsTdFiles", ":CastInterfacesTdFiles", ":ControlFlowInterfacesTdFiles", @@ -10582,7 +10582,7 @@ cc_library( ":DialectUtils", ":IR", ":InferTypeOpInterface", - ":Mem2RegInterfaces", + ":MemorySlotInterfaces", ":MemRefBaseIncGen", ":MemRefOpsIncGen", ":ShapedOpInterfaces", |