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* [mips] Guard indirect and tailcall pseudo instructions correctly.Simon Dardis2017-11-083-11/+23
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-089-13/+13
* [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 versionSimon Dardis2017-11-068-5/+51
* [mips] Fix PR35140Simon Dardis2017-11-061-4/+4
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-036-6/+6
* [mips] Match 'ins' and its' variants with C++ codeSimon Dardis2017-11-035-12/+70
* [mips] Use register scavenging with MSA.Simon Dardis2017-11-022-24/+19
* [mips] Fix (dis)assembly of abs.fmt for micromipsSimon Dardis2017-10-262-7/+16
* [mips] Fix PR35071Simon Dardis2017-10-261-13/+12
* [mips] Clean up some whitespace (NFC).Simon Dardis2017-10-251-1/+1
* [MC] Adding code padding for performance stability - infrastructure. NFC.Omer Paparo Bivas2017-10-241-0/+1
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-202-27/+26
* [mips] Fix analyzeBranch to handle debug dataSimon Dardis2017-10-181-1/+7
* Untabify.NAKAMURA Takumi2017-10-181-5/+5
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-163-14/+21
* [mips] Provide alternate predicates for constant synthesisStefan Maksimovic2017-10-162-17/+30
* Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman2017-10-151-1/+1
* Remove unused variablesVitaly Buka2017-10-153-3/+0
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-123-5/+5
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-123-5/+5
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-121-1/+1
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-115-19/+28
* [mips] Add support for parsing target specific flags for MIRSimon Dardis2017-10-112-0/+42
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+1
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-115-18/+30
* [mips] Correct the instruction predicates for microMIPSr3Simon Dardis2017-10-101-205/+224
* [MC] Thread unique_ptr<MCObjectWriter> through the create.*ObjectWriterLang Hames2017-10-104-6/+11
* [mips] Duplicate the reciprocal instruction definitions for FP32Simon Dardis2017-10-102-10/+34
* [mips] Partially fix PR34391Simon Dardis2017-10-101-4/+11
* [MC] Plumb unique_ptr<MCELFObjectTargetWriter> through createELFObjectWriter toLang Hames2017-10-091-3/+3
* [mips] implement .set dspr2 directivePetar Jovanovic2017-10-053-0/+14
* [mips] Place certain 64 bit FPU instructions in their own decoder namespaceSimon Dardis2017-10-054-25/+34
* [mips] Enable spilling and reloading of the dsp register set.Simon Dardis2017-10-033-0/+17
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-292-26/+27
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-09-292-27/+26
* [mips] Add missing license info, formatting changes. NFCISimon Dardis2017-09-291-30/+47
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-292-26/+27
* [mips] Remove codegen support for branch likely instructions.Simon Dardis2017-09-282-18/+49
* Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with int...Alex Bradbury2017-09-282-45/+0
* [mips] clang-format MipsTargetMachine.cppAlexander Richardson2017-09-221-3/+3
* [mips] Do not pass redundant IsN64 flag to MCELFObjectTargetWriter. NFCSimon Atanasyan2017-09-211-5/+4
* [mips] Fix relocation record format and ELF header for N32 ABISimon Atanasyan2017-09-215-10/+21
* [mips] Fix calculation of a branch instruction offset to escape left shift of...Simon Atanasyan2017-09-201-3/+3
* [DAGCombiner] fold assertzexts separated by truncSanjay Patel2017-09-181-33/+0
* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-145-43/+162
* [mips] Implement the 'dins' aliases.Simon Dardis2017-09-145-25/+139
* Test commit.Aleksandar Beserminji2017-09-141-1/+1
* [mips] Pick the right variant of DINS upfront and enable target instruction v...Simon Dardis2017-09-148-44/+119
* [mips] correct operand range for DINSM instructionPetar Jovanovic2017-09-131-1/+1
* [mips] handle UImm16_AltRelaxed match typePetar Jovanovic2017-09-121-0/+1
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