| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0 | Alex Bradbury | 2017-11-08 | 1 | -3/+1 |
| * | [RISCV] Add missing hunk from r316188 | Alex Bradbury | 2017-10-19 | 1 | -1/+3 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -2/+5 |
| * | [RISCV] Prepare for the use of variable-sized register classes | Alex Bradbury | 2017-10-19 | 1 | -5/+23 |
| * | [RISCV] Add basic RISCVAsmParser | Alex Bradbury | 2017-08-08 | 1 | -0/+5 |
| * | [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td | Alex Bradbury | 2016-11-01 | 1 | -0/+27 |
 |
index : delta/llvm.git | |
| github.com: llvm/llvm-project.git |
| summaryrefslogtreecommitdiff |