| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are ... | Cong Hou | 2015-09-18 | 1 | -3/+0 |
| * | ARM: Enable MachineScheduler and disable PostRAScheduler for swift. | Matthias Braun | 2015-07-17 | 1 | -8/+8 |
| * | Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift." | Adam Nemet | 2015-07-17 | 1 | -8/+8 |
| * | ARM: Enable MachineScheduler and disable PostRAScheduler for swift. | Matthias Braun | 2015-07-17 | 1 | -8/+8 |
| * | [opaque pointer type] Add textual IR support for explicit type parameter to l... | David Blaikie | 2015-02-27 | 1 | -8/+8 |
| * | [opaque pointer type] Add textual IR support for explicit type parameter to g... | David Blaikie | 2015-02-27 | 1 | -12/+12 |
| * | Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f... | Stephen Lin | 2013-07-14 | 1 | -1/+1 |
| * | test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts. | NAKAMURA Takumi | 2012-01-13 | 1 | -0/+1 |
| * | DAGCombine's logic for forming pre- and post- indexed loads / stores were being | Evan Cheng | 2012-01-13 | 1 | -0/+95 |
 |
index : delta/llvm.git | |
| github.com: llvm/llvm-project.git |
| summaryrefslogtreecommitdiff |