diff options
author | Mike Pall <mike> | 2011-12-10 00:18:19 +0100 |
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committer | Mike Pall <mike> | 2011-12-10 00:18:19 +0100 |
commit | 60b8e9e2fbc2df3281bc9fac714aad3fd7578717 (patch) | |
tree | 1fd2566fd1dbda9bfed317ffa5396855d2dbdc78 /src/lj_asm_arm.h | |
parent | 2591b4524ab2e27702bfc1f41b87348aab66e802 (diff) | |
download | luajit2-60b8e9e2fbc2df3281bc9fac714aad3fd7578717.tar.gz |
ARM: Fix stack check for spilled BASE in parent.
Diffstat (limited to 'src/lj_asm_arm.h')
-rw-r--r-- | src/lj_asm_arm.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/lj_asm_arm.h b/src/lj_asm_arm.h index 0ab4917e..24b49e69 100644 --- a/src/lj_asm_arm.h +++ b/src/lj_asm_arm.h @@ -1422,8 +1422,9 @@ static void asm_stack_check(ASMState *as, BCReg topslot, Reg pbase; uint32_t k; if (irp) { - if (ra_hasreg(irp->r)) { + if (!ra_hasspill(irp->s)) { pbase = irp->r; + lua_assert(ra_hasreg(pbase)); } else if (allow) { pbase = rset_pickbot(allow); } else { @@ -1442,14 +1443,11 @@ static void asm_stack_check(ASMState *as, BCReg topslot, (int32_t)offsetof(lua_State, maxstack)); if (irp) { /* Must not spill arbitrary registers in head of side trace. */ int32_t i = i32ptr(&J2G(as->J)->jit_L); - if (ra_noreg(irp->r)) { - lua_assert(ra_hasspill(irp->s)); - emit_lso(as, ARMI_LDR, RID_RET, RID_SP, sps_scale(irp->s)); - } + if (ra_hasspill(irp->s)) + emit_lso(as, ARMI_LDR, pbase, RID_SP, sps_scale(irp->s)); emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP, (i & 4095)); - if (ra_noreg(irp->r)) { + if (ra_hasspill(irp->s) && !allow) emit_lso(as, ARMI_STR, RID_RET, RID_SP, 0); /* Save temp. register. */ - } emit_loadi(as, RID_TMP, (i & ~4095)); } else { emit_getgl(as, RID_TMP, jit_L); |