diff options
| author | Sagar Ghuge <sagar.ghuge@intel.com> | 2023-05-16 14:39:12 -0700 |
|---|---|---|
| committer | Sagar Ghuge <sagar.ghuge@intel.com> | 2023-05-17 10:05:44 -0700 |
| commit | 4f9314588fa76ada7dbdae2bfbc5a7870c9c7cd5 (patch) | |
| tree | ddc275d8f17961d7dce80dd242b1c39bb191a287 | |
| parent | 688ee02864d52101a31886f9d762e6d8d13bc3c2 (diff) | |
| download | mesa-4f9314588fa76ada7dbdae2bfbc5a7870c9c7cd5.tar.gz | |
iris: Set CS stall bit during HIZ_CCS_WT surface fast clear
It make sense to enable CS stall so that it guarantees that the fast
clear will start after tile cache flush has completed.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23063>
| -rw-r--r-- | src/gallium/drivers/iris/iris_clear.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 253a04a2be0..e7e896dc7c5 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -481,9 +481,13 @@ fast_clear_depth(struct iris_context *ice, * * There may have been a write to this depth buffer. Flush it from the * tile cache just in case. + * + * Set CS stall bit to guarantee that the fast clear starts the execution + * after the tile cache flush completed. */ iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear", PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_CS_STALL | PIPE_CONTROL_TILE_CACHE_FLUSH); } |