6 files changed, 22 insertions, 4 deletions

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index 4636a7398c7..b55ca64ab39 100644
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -285,6 +285,10 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
       compiler->nir_options.force_indirect_unrolling = nir_var_all;
    }
 
+   if (options->lower_base_vertex) {
+      compiler->nir_options.lower_base_vertex = true;
+   }
+
    /* 16-bit ALU op generation is mostly controlled by frontend compiler options, but
     * this core NIR option enables some optimizations of 16-bit operations.
     */
diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h
index 4abd574ff80..daf966a993a 100644
--- a/src/freedreno/ir3/ir3_compiler.h
+++ b/src/freedreno/ir3/ir3_compiler.h
@@ -67,6 +67,9 @@ struct ir3_compiler_options {
 
    /* True if 16-bit descriptors are used for both 16-bit and 32-bit access. */
    bool storage_16bit;
+
+  /* If base_vertex should be lowered in nir */
+  bool lower_base_vertex;
 };
 
 struct ir3_compiler {
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index f8316f417a4..c457d4db575 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -2204,6 +2204,12 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
       }
       dst[0] = ctx->basevertex;
       break;
+   case nir_intrinsic_load_is_indexed_draw:
+      if (!ctx->is_indexed_draw) {
+         ctx->is_indexed_draw = create_driver_param(ctx, IR3_DP_IS_INDEXED_DRAW);
+      }
+      dst[0] = ctx->is_indexed_draw;
+      break;
    case nir_intrinsic_load_draw_id:
       if (!ctx->draw_id) {
          ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
diff --git a/src/freedreno/ir3/ir3_context.h b/src/freedreno/ir3/ir3_context.h
index 0085d8abdbf..22c7b1b3cdf 100644
--- a/src/freedreno/ir3/ir3_context.h
+++ b/src/freedreno/ir3/ir3_context.h
@@ -85,7 +85,7 @@ struct ir3_context {
 
    /* For vertex shaders, keep track of the system values sources */
    struct ir3_instruction *vertex_id, *basevertex, *instance_id, *base_instance,
-      *draw_id, *view_index;
+      *draw_id, *view_index, *is_indexed_draw;
 
    /* For fragment shaders: */
    struct ir3_instruction *samp_id, *samp_mask_in;
diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index b1cf668421e..da842e01c5c 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -864,6 +864,10 @@ ir3_nir_scan_driver_consts(struct ir3_compiler *compiler, nir_shader *shader, st
                layout->num_driver_params =
                   MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
                break;
+            case nir_intrinsic_load_is_indexed_draw:
+               layout->num_driver_params =
+                  MAX2(layout->num_driver_params, IR3_DP_IS_INDEXED_DRAW + 1);
+               break;
             case nir_intrinsic_load_base_instance:
                layout->num_driver_params =
                   MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 25125332e7c..6c921732c1a 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -69,11 +69,12 @@ enum ir3_driver_param {
    IR3_DP_VTXID_BASE = 1,
    IR3_DP_INSTID_BASE = 2,
    IR3_DP_VTXCNT_MAX = 3,
+   IR3_DP_IS_INDEXED_DRAW = 4,  /* Note: boolean, ie. 0 or ~0 */
    /* user-clip-plane components, up to 8x vec4's: */
-   IR3_DP_UCP0_X = 4,
+   IR3_DP_UCP0_X = 5,
    /* .... */
-   IR3_DP_UCP7_W = 35,
-   IR3_DP_VS_COUNT = 36, /* must be aligned to vec4 */
+   IR3_DP_UCP7_W = 36,
+   IR3_DP_VS_COUNT = 40, /* must be aligned to vec4 */
 
    /* TCS driver params: */
    IR3_DP_HS_DEFAULT_OUTER_LEVEL_X = 0,