[src/sub1sp.c] Completed r13506: added MPFR_ASSERTD to justify the

new code and give more information to the compiler; added comments
about this optimization issue.

git-svn-id: svn://scm.gforge.inria.fr/svn/mpfr/trunk@13507 280ebfd0-de03-0410-8827-d642c229c3f4

1 files changed, 11 insertions, 0 deletions

diff --git a/src/sub1sp.c b/src/sub1sp.c
index 5c1c74ffd..5d6a2de28 100644
--- a/src/sub1sp.c
+++ b/src/sub1sp.c
@@ -120,6 +120,11 @@ mpfr_sub1sp1 (mpfr_ptr a, mpfr_srcptr b, mpfr_srcptr c, mpfr_rnd_t rnd_mode,
 
   if (bx == cx)
     {
+      MPFR_ASSERTD (bp[0] >= MPFR_LIMB_HIGHBIT);
+      MPFR_ASSERTD (cp[0] >= MPFR_LIMB_HIGHBIT);
+      /* Thus, mathematically, the signed difference is between
+         1 - MPFR_LIMB_HIGHBIT and MPFR_LIMB_HIGHBIT - 1, and the
+         most significant bit is equivalent to the usual sign bit. */
       a0 = bp[0] - cp[0];
       if (a0 == 0) /* result is zero */
         {
@@ -132,6 +137,12 @@ mpfr_sub1sp1 (mpfr_ptr a, mpfr_srcptr b, mpfr_srcptr c, mpfr_rnd_t rnd_mode,
         }
       else if (a0 >= MPFR_LIMB_HIGHBIT) /* borrow: |c| > |b| */
         {
+          /* Note: The test before r13506 was a0 > bp[0], which should be
+             easier to optimize than a0 >= MPFR_LIMB_HIGHBIT on processors
+             with condition flags, i.e. the test should be a no-op as the
+             flag should have been obtained form the subtraction above.
+             TODO: revert the test in the future, once compilers have
+             improved? */
           MPFR_SET_OPPOSITE_SIGN (a, b);
           a0 = -a0;
         }