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| author | H. Peter Anvin (Intel) <hpa@zytor.com> | 2020-06-22 13:44:54 -0700 |
|---|---|---|
| committer | H. Peter Anvin (Intel) <hpa@zytor.com> | 2020-06-22 13:52:02 -0700 |
| commit | d85a6101d731083fa3faae901426e731881f52d4 (patch) | |
| tree | 13b7b70e699b681abea591647f87a2c0efc200a9 /asm | |
| parent | 6e9554f0677752fd41674a0e20623d83b381d6da (diff) | |
| download | nasm-d85a6101d731083fa3faae901426e731881f52d4.tar.gz | |
BR 3392681: handle a64 instruction patters correctly
The a64 instruction patterns would incorrectly force REX to zero at a
point where REX prefixes have already been assigned. This is not only
incorrect in case of instructions which can use high registers, but it
causes an assertion failure. It happened to work for J*CXZ and LOOP*.
Reported-by: Philip Lantz <philip.lantz@intel.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Diffstat (limited to 'asm')
| -rw-r--r-- | asm/assemble.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/asm/assemble.c b/asm/assemble.c index 7a0830ca..e5d5682c 100644 --- a/asm/assemble.c +++ b/asm/assemble.c @@ -2083,7 +2083,6 @@ static void gencode(struct out_data *data, insn *ins) break; case 0313: - ins->rex = 0; break; case4(0314): |