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| author | Victor van den Elzen <victor.vde@gmail.com> | 2008-04-23 15:05:31 +0200 |
|---|---|---|
| committer | Victor van den Elzen <victor.vde@gmail.com> | 2008-05-21 12:42:46 +0200 |
| commit | 82fa68acecf2f7e1d382501fbcff820883ec2ef4 (patch) | |
| tree | 46a69ed47dd5f38613f0d78a90bcfd706bcbe292 /test/lar_lsl.asm | |
| parent | 533385ace56de28f3ac0b11c762f510cb19b4e90 (diff) | |
| download | nasm-82fa68acecf2f7e1d382501fbcff820883ec2ef4.tar.gz | |
Configure tests to be performed automatically
Diffstat (limited to 'test/lar_lsl.asm')
| -rw-r--r-- | test/lar_lsl.asm | 246 |
1 files changed, 124 insertions, 122 deletions
diff --git a/test/lar_lsl.asm b/test/lar_lsl.asm index 69c56fc9..7c7b82ca 100644 --- a/test/lar_lsl.asm +++ b/test/lar_lsl.asm @@ -1,122 +1,124 @@ -; LAR/LSL
-;---------
-
-; 1x ; = invalid due to lack of REX
-; 3x ; = invalid due to Mw
-
-%macro m 1
-
- bits 16
-
- %1 ax, ax
- %1 ax,eax
-; %1 ax,rax
-
- %1 eax, ax
- %1 eax,eax
-; %1 eax,rax
-
-; %1 rax, ax
-; %1 rax,eax
-; %1 rax,rax
-
- %1 ax, [0]
- %1 ax, word [0]
-;;; %1 ax,dword [0]
-; %1 ax,qword [0]
-
- %1 eax, [0]
- %1 eax, word [0]
-;;; %1 eax,dword [0]
-; %1 eax,qword [0]
-
-; %1 rax, [0]
-; %1 rax, word [0]
-; %1 rax,dword [0]
-; %1 rax,qword [0]
-
- bits 32
-
- %1 ax, ax
- %1 ax,eax
-; %1 ax,rax
-
- %1 eax, ax
- %1 eax,eax
-; %1 eax,rax
-
-; %1 rax, ax
-; %1 rax,eax
-; %1 rax,rax
-
- %1 ax, [0]
- %1 ax, word [0]
-;;; %1 ax,dword [0]
-; %1 ax,qword [0]
-
- %1 eax, [0]
- %1 eax, word [0]
-;;; %1 eax,dword [0]
-; %1 eax,qword [0]
-
-; %1 rax, [0]
-; %1 rax, word [0]
-; %1 rax,dword [0]
-; %1 rax,qword [0]
-
- bits 64
-
- %1 ax, ax
- %1 ax,eax
- %1 ax,rax ; $TODO: shouldn't emit REX.W $
-
- %1 eax, ax
- %1 eax,eax
- %1 eax,rax ; $TODO: shouldn't emit REX.W $
-
- %1 rax, ax
- %1 rax,eax
- %1 rax,rax
-
- %1 ax, [0]
- %1 ax, word [0]
-;;; %1 ax,dword [0]
-;;; %1 ax,qword [0]
-
- %1 eax, [0]
- %1 eax, word [0]
-;;; %1 eax,dword [0]
-;;; %1 eax,qword [0]
-
- %1 rax, [0]
- %1 rax, word [0]
-;;; %1 rax,dword [0]
-;;; %1 rax,qword [0]
-
-%endmacro
-
-m lar
-
-m lsl
-
-bits 16
-lar ax,[ si]
-lar ax,[esi]
-bits 32
-lar ax,[ si]
-lar ax,[esi]
-bits 64
-lar ax,[esi]
-lar ax,[rsi]
-
-bits 16
-lsl ax,[ si]
-lsl ax,[esi]
-bits 32
-lsl ax,[ si]
-lsl ax,[esi]
-bits 64
-lar ax,[esi]
-lsl ax,[rsi]
-
-; EOF
+;Testname=test; Arguments=-fbin -olar_lsl.bin; Files=.stdout .stderr lar_lsl.bin + +; LAR/LSL +;--------- + +; 1x ; = invalid due to lack of REX +; 3x ; = invalid due to Mw + +%macro m 1 + + bits 16 + + %1 ax, ax + %1 ax,eax +; %1 ax,rax + + %1 eax, ax + %1 eax,eax +; %1 eax,rax + +; %1 rax, ax +; %1 rax,eax +; %1 rax,rax + + %1 ax, [0] + %1 ax, word [0] +;;; %1 ax,dword [0] +; %1 ax,qword [0] + + %1 eax, [0] + %1 eax, word [0] +;;; %1 eax,dword [0] +; %1 eax,qword [0] + +; %1 rax, [0] +; %1 rax, word [0] +; %1 rax,dword [0] +; %1 rax,qword [0] + + bits 32 + + %1 ax, ax + %1 ax,eax +; %1 ax,rax + + %1 eax, ax + %1 eax,eax +; %1 eax,rax + +; %1 rax, ax +; %1 rax,eax +; %1 rax,rax + + %1 ax, [0] + %1 ax, word [0] +;;; %1 ax,dword [0] +; %1 ax,qword [0] + + %1 eax, [0] + %1 eax, word [0] +;;; %1 eax,dword [0] +; %1 eax,qword [0] + +; %1 rax, [0] +; %1 rax, word [0] +; %1 rax,dword [0] +; %1 rax,qword [0] + + bits 64 + + %1 ax, ax + %1 ax,eax + %1 ax,rax ; $TODO: shouldn't emit REX.W $ + + %1 eax, ax + %1 eax,eax + %1 eax,rax ; $TODO: shouldn't emit REX.W $ + + %1 rax, ax + %1 rax,eax + %1 rax,rax + + %1 ax, [0] + %1 ax, word [0] +;;; %1 ax,dword [0] +;;; %1 ax,qword [0] + + %1 eax, [0] + %1 eax, word [0] +;;; %1 eax,dword [0] +;;; %1 eax,qword [0] + + %1 rax, [0] + %1 rax, word [0] +;;; %1 rax,dword [0] +;;; %1 rax,qword [0] + +%endmacro + +m lar + +m lsl + +bits 16 +lar ax,[ si] +lar ax,[esi] +bits 32 +lar ax,[ si] +lar ax,[esi] +bits 64 +lar ax,[esi] +lar ax,[rsi] + +bits 16 +lsl ax,[ si] +lsl ax,[esi] +bits 32 +lsl ax,[ si] +lsl ax,[esi] +bits 64 +lar ax,[esi] +lsl ax,[rsi] + +; EOF |