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| author | H. Peter Anvin <hpa@zytor.com> | 2012-03-05 22:37:21 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2012-03-05 22:37:21 -0800 |
| commit | b106ba161fc3b4c9e1740d6f8990211aff251199 (patch) | |
| tree | daec0d63973dacdc88dd1f65b86ce7c1b680593e /test/movd64.asm | |
| parent | 9d91ff5b123aafbd92702e2a1f35661d9cc9bdb0 (diff) | |
| download | nasm-b106ba161fc3b4c9e1740d6f8990211aff251199.tar.gz | |
Try again to fix our handling of MOVD/MOVQ
Try to implement the handling of MOVD as attempted in checkin:
70712c0df6c437c50452c4997aa2e3de5a0e0299
and reverted in:
d279fbbd80aab6f79584249629a4aea90b851458
due to BR3392199. This time make sure to use the SX flag to only
match when a size is explicitly given, and also don't duplicate the 0F
6F/7F opcodes, which are documented as MOVQ by AMD as well as Intel.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'test/movd64.asm')
| -rw-r--r-- | test/movd64.asm | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/movd64.asm b/test/movd64.asm new file mode 100644 index 00000000..b328c349 --- /dev/null +++ b/test/movd64.asm @@ -0,0 +1,15 @@ + bits 64 + + movd r8d, mm1 + movd r8, mm1 + movq r8, mm1 + + movd [rax], mm1 + movq [rax], mm1 + movd dword [rax], mm1 +; movq dword [rax], mm1 + movd qword [rax], mm1 + movq qword [rax], mm1 + +; movd mm2, mm1 + movq mm2, mm1 |