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| author | H. Peter Anvin <hpa@linux.intel.com> | 2018-02-06 14:43:07 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2018-02-06 14:43:07 -0800 |
| commit | a7ecf2646d6c80b994be7d340140379d580050cf (patch) | |
| tree | 50fc3d8fb36d4a96dff236ddaf2ee8420f27f020 /test/vaesenc.asm | |
| parent | 4d7e680cb015e5d77764ff1cc83a417ecb73e31b (diff) | |
| download | nasm-a7ecf2646d6c80b994be7d340140379d580050cf.tar.gz | |
iflag: automatically assign values, saner handling of CPU levels
Automatically assign values to the instruction flags; we ended up with
a case where pushing flags into the next dword caused comparison
failures due to other places in the code explicitly comparing
field[3].
This creates necessary defines for this not to happen; it also cleans
up a fair bit of the iflag code.
This resolves BR 3392454.
Reported-by: Thomasz Kantecki <tomasz.kantecki@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'test/vaesenc.asm')
| -rw-r--r-- | test/vaesenc.asm | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/test/vaesenc.asm b/test/vaesenc.asm new file mode 100644 index 00000000..5a629ab0 --- /dev/null +++ b/test/vaesenc.asm @@ -0,0 +1,6 @@ +;; BR 3392454 + + bits 64 + aesenc xmm0,xmm4 + vaesenc zmm0,zmm0,zmm4 + vpclmullqlqdq zmm1,zmm1,zmm5 |