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| author | H. Peter Anvin (Intel) <hpa@zytor.com> | 2018-06-25 14:35:05 -0700 |
|---|---|---|
| committer | H. Peter Anvin (Intel) <hpa@zytor.com> | 2018-06-25 14:35:05 -0700 |
| commit | 26b810176f939f5c7f1e6364ed5901283d1a576b (patch) | |
| tree | 72d98a184afccf0ec363e3a3adcb03ce6ea3e3c7 /x86 | |
| parent | b6b4b5d5460cfd4157c570546d92f02dbc3c2698 (diff) | |
| download | nasm-26b810176f939f5c7f1e6364ed5901283d1a576b.tar.gz | |
insns.dat: add PTWRITE instruction
Add PTWRITE instruction. It is worth noting that we should
be able to do "ptwrite [eax]" in 32-bit mode, but the instruction
selector doesn't currently handle that well in a way that doesn't make
64-bit mode very confusing.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Diffstat (limited to 'x86')
| -rw-r--r-- | x86/insns.dat | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/x86/insns.dat b/x86/insns.dat index cabd9bd6..96295dc1 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -5197,6 +5197,10 @@ PCOMMIT void [ 66 0f ae f8] ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD +;# Processor trace write +PTWRITE rm32 [m: np 0f ae /4] FUTURE +PTWRITE rm64 [m: o64 np 0f ae /4] X64,FUTURE + ;# Instructions from the Intel Instruction Set Extensions, ;# doc 319433-034 May 2018 CLDEMOTE mem [m: np 0f 1c /0] FUTURE |