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| author | H. Peter Anvin <hpa@zytor.com> | 2020-06-01 16:03:54 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2020-06-01 16:03:54 -0700 |
| commit | 7002bb76a3b6c43848dac2e7defcf95c46040517 (patch) | |
| tree | f926b00e039542f3c97f412af5c8e0f8f4021aed /x86 | |
| parent | 5b4de52083512d1676b54666a701c931d04b866a (diff) | |
| download | nasm-7002bb76a3b6c43848dac2e7defcf95c46040517.tar.gz | |
BR 3392674: fix handling of {ud1,ud2b} <reg>,<reg>
We need the instruction table to contain the correct information for
both the reg and the rm field in the various modes.
Reported-by: <fasdfqwer@mail.com>
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Diffstat (limited to 'x86')
| -rw-r--r-- | x86/insns.dat | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/x86/insns.dat b/x86/insns.dat index c142a61d..e8117241 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -1402,14 +1402,14 @@ UD0 void [ 0f ff] 186,OBSOLETE UD0 reg16,rm16 [rm: o16 0f ff /r] 186 UD0 reg32,rm32 [rm: o32 0f ff /r] 186 UD0 reg64,rm64 [rm: o64 0f ff /r] 186 -UD1 reg,rm16 [rm: o16 0f b9 /r] 186 -UD1 reg,rm32 [rm: o32 0f b9 /r] 186 -UD1 reg,rm64 [rm: o64 0f b9 /r] 186 +UD1 reg16,rm16 [rm: o16 0f b9 /r] 186 +UD1 reg32,rm32 [rm: o32 0f b9 /r] 186 +UD1 reg64,rm64 [rm: o64 0f b9 /r] 186 UD1 void [ 0f b9] 186,ND UD2B void [ 0f b9] 186,ND -UD2B reg,rm16 [rm: o16 0f b9 /r] 186,ND -UD2B reg,rm32 [rm: o32 0f b9 /r] 186,ND -UD2B reg,rm64 [rm: o64 0f b9 /r] 186,ND +UD2B reg16,rm16 [rm: o16 0f b9 /r] 186,ND +UD2B reg32,rm32 [rm: o32 0f b9 /r] 186,ND +UD2B reg64,rm64 [rm: o64 0f b9 /r] 186,ND UD2 void [ 0f 0b] 186 UD2A void [ 0f 0b] 186,ND UMOV mem,reg8 [mr: np 0f 10 /r] 386,UNDOC,SM,ND |