diff options
| author | Maamoun TK <maamoun.tk@googlemail.com> | 2020-09-19 08:32:29 +0300 |
|---|---|---|
| committer | Niels Möller <nisse@lysator.liu.se> | 2020-09-23 19:19:13 +0200 |
| commit | 0d70c31c804632cd3b9006ce2f723b0f54c6a8d0 (patch) | |
| tree | 7b00917e64c861d158a8b7a0685521b7a9c3b24d /powerpc64/machine.m4 | |
| parent | 2e6c93ca0f1d3814411b009c90abd2d70e71edea (diff) | |
| download | nettle-0d70c31c804632cd3b9006ce2f723b0f54c6a8d0.tar.gz | |
"PowerPC64" Use explicit register names
This patch is built upon ppc-m4-macrology.patch. Using explicit register
names is working as expected now.
Diffstat (limited to 'powerpc64/machine.m4')
| -rw-r--r-- | powerpc64/machine.m4 | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/powerpc64/machine.m4 b/powerpc64/machine.m4 index ae161d79..f867ec01 100644 --- a/powerpc64/machine.m4 +++ b/powerpc64/machine.m4 @@ -24,7 +24,10 @@ define(`EPILOGUE', C Get vector-scalar register from vector register C VSR(VR) -define(`VSR',`32+$1') +define(`VSR',`ifelse(ASM_PPC_WANT_R_REGISTERS,no, +`eval(32+$1)', +``vs'eval(32+substr($1,1,len($1)))' +)') C Load the quadword in DATA_SRC storage into C VEC_DST. GPR is general-purpose register @@ -32,19 +35,19 @@ C used to obtain the effective address of C DATA_SRC storage. C DATA_LOAD_VEC(VEC_DST, DATA_SRC, GPR) define(`DATA_LOAD_VEC', -`ld $3,$2@got(2) +`ld $3,$2@got(r2) lvx $1,0,$3') dnl Usage: r0 ... r31, cr0 ... cr7 dnl dnl Registers names, either left as "r0" etc or mapped to plain 0 etc, -dnl according to the result of the GMP_ASM_POWERPC_REGISTERS configure +dnl according to the result of the ASM_PPC_WANT_R_REGISTERS configure dnl test. ifelse(ASM_PPC_WANT_R_REGISTERS,no,` forloop(i,0,31,`deflit(`r'i,i)') forloop(i,0,31,`deflit(`v'i,i)') +forloop(i,0,63,`deflit(`vs'i,i)') forloop(i,0,31,`deflit(`f'i,i)') forloop(i,0,7, `deflit(`cr'i,i)') ') - |