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authorMichaël Zasso <targos@protonmail.com>2019-11-08 15:39:11 +0100
committerMichaël Zasso <targos@protonmail.com>2019-11-08 15:46:25 +0100
commit6ca81ad72a3c6fdf16c683335be748f22aaa9a0d (patch)
tree33c8ee75f729aed76c2c0b89c63f9bf1b4dd66aa /deps/v8/src/codegen/arm64/assembler-arm64-inl.h
parent1eee0b8bf8bba39b600fb16a9223e545e3bac2bc (diff)
downloadnode-new-6ca81ad72a3c6fdf16c683335be748f22aaa9a0d.tar.gz
deps: update V8 to 7.9.317.20
PR-URL: https://github.com/nodejs/node/pull/30020 Reviewed-By: Colin Ihrig <cjihrig@gmail.com> Reviewed-By: Jiawen Geng <technicalcute@gmail.com> Reviewed-By: Anna Henningsen <anna@addaleax.net> Reviewed-By: Matteo Collina <matteo.collina@gmail.com>
Diffstat (limited to 'deps/v8/src/codegen/arm64/assembler-arm64-inl.h')
-rw-r--r--deps/v8/src/codegen/arm64/assembler-arm64-inl.h20
1 files changed, 15 insertions, 5 deletions
diff --git a/deps/v8/src/codegen/arm64/assembler-arm64-inl.h b/deps/v8/src/codegen/arm64/assembler-arm64-inl.h
index baae106c1c..ce34da7dc2 100644
--- a/deps/v8/src/codegen/arm64/assembler-arm64-inl.h
+++ b/deps/v8/src/codegen/arm64/assembler-arm64-inl.h
@@ -54,14 +54,12 @@ inline bool CPURegister::IsSP() const {
}
inline void CPURegList::Combine(const CPURegList& other) {
- DCHECK(IsValid());
DCHECK(other.type() == type_);
DCHECK(other.RegisterSizeInBits() == size_);
list_ |= other.list();
}
inline void CPURegList::Remove(const CPURegList& other) {
- DCHECK(IsValid());
if (other.type() == type_) {
list_ &= ~other.list();
}
@@ -84,13 +82,12 @@ inline void CPURegList::Remove(const CPURegister& other1,
}
inline void CPURegList::Combine(int code) {
- DCHECK(IsValid());
DCHECK(CPURegister::Create(code, size_, type_).IsValid());
list_ |= (1ULL << code);
+ DCHECK(IsValid());
}
inline void CPURegList::Remove(int code) {
- DCHECK(IsValid());
DCHECK(CPURegister::Create(code, size_, type_).IsValid());
list_ &= ~(1ULL << code);
}
@@ -311,6 +308,18 @@ Operand Operand::ToExtendedRegister() const {
return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
}
+Operand Operand::ToW() const {
+ if (IsShiftedRegister()) {
+ DCHECK(reg_.Is64Bits());
+ return Operand(reg_.W(), shift(), shift_amount());
+ } else if (IsExtendedRegister()) {
+ DCHECK(reg_.Is64Bits());
+ return Operand(reg_.W(), extend(), shift_amount());
+ }
+ DCHECK(IsImmediate());
+ return *this;
+}
+
Immediate Operand::immediate_for_heap_object_request() const {
DCHECK((heap_object_request().kind() == HeapObjectRequest::kHeapNumber &&
immediate_.rmode() == RelocInfo::FULL_EMBEDDED_OBJECT) ||
@@ -711,7 +720,8 @@ void RelocInfo::set_target_object(Heap* heap, HeapObject target,
Assembler::set_target_address_at(pc_, constant_pool_, target.ptr(),
icache_flush_mode);
}
- if (write_barrier_mode == UPDATE_WRITE_BARRIER && !host().is_null()) {
+ if (write_barrier_mode == UPDATE_WRITE_BARRIER && !host().is_null() &&
+ !FLAG_disable_write_barriers) {
WriteBarrierForCode(host(), this, target);
}
}