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authorMichaël Zasso <targos@protonmail.com>2017-10-18 15:03:02 -0700
committerMichaël Zasso <targos@protonmail.com>2017-10-18 17:01:41 -0700
commit3d1b3df9486c0e7708065257f7311902f6b7b366 (patch)
treecb051bdeaead11e06dcd97725783e0f113afb1bf /deps/v8/src/s390/simulator-s390.cc
parente2cddbb8ccdb7b3c4a40c8acc630f68703bc77b5 (diff)
downloadnode-new-3d1b3df9486c0e7708065257f7311902f6b7b366.tar.gz
deps: update V8 to 6.2.414.32
PR-URL: https://github.com/nodejs/node/pull/15362 Reviewed-By: Myles Borins <myles.borins@gmail.com> Reviewed-By: Colin Ihrig <cjihrig@gmail.com> Reviewed-By: Matteo Collina <matteo.collina@gmail.com> Reviewed-By: Ben Noordhuis <info@bnoordhuis.nl>
Diffstat (limited to 'deps/v8/src/s390/simulator-s390.cc')
-rw-r--r--deps/v8/src/s390/simulator-s390.cc20
1 files changed, 10 insertions, 10 deletions
diff --git a/deps/v8/src/s390/simulator-s390.cc b/deps/v8/src/s390/simulator-s390.cc
index 0888beff2c..1900117502 100644
--- a/deps/v8/src/s390/simulator-s390.cc
+++ b/deps/v8/src/s390/simulator-s390.cc
@@ -13,9 +13,9 @@
#include "src/base/once.h"
#include "src/codegen.h"
#include "src/disasm.h"
+#include "src/frame-constants.h"
#include "src/runtime/runtime-utils.h"
#include "src/s390/constants-s390.h"
-#include "src/s390/frames-s390.h"
#include "src/s390/simulator-s390.h"
#if defined(USE_SIMULATOR)
@@ -23,7 +23,7 @@
namespace v8 {
namespace internal {
-const auto GetRegConfig = RegisterConfiguration::Crankshaft;
+const auto GetRegConfig = RegisterConfiguration::Default;
// This macro provides a platform independent use of sscanf. The reason for
// SScanF not being implemented in a platform independent way through
@@ -2408,7 +2408,7 @@ void Simulator::PrintStopInfo(uint32_t code) {
#define CheckOverflowForIntSub(src1, src2, type) \
OverflowFromSigned<type>(src1 - src2, src1, src2, false);
-// Method for checking overflow on unsigned addtion
+// Method for checking overflow on unsigned addition
#define CheckOverflowForUIntAdd(src1, src2) \
((src1) + (src2) < (src1) || (src1) + (src2) < (src2))
@@ -2514,7 +2514,7 @@ void Simulator::Execute() {
}
} else {
// FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
- // we reach the particular instuction count.
+ // we reach the particular instruction count.
while (program_counter != end_sim_pc) {
Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
if (icount_ == ::v8::internal::FLAG_stop_sim_at) {
@@ -4177,7 +4177,7 @@ EVALUATE(STM) {
// Store Multiple 32-bits.
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;
@@ -4259,7 +4259,7 @@ EVALUATE(LM) {
// Store Multiple 32-bits.
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;
@@ -8782,7 +8782,7 @@ EVALUATE(LMG) {
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;
@@ -8948,7 +8948,7 @@ EVALUATE(STMG) {
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;
@@ -9159,7 +9159,7 @@ EVALUATE(STMY) {
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;
@@ -9186,7 +9186,7 @@ EVALUATE(LMY) {
int offset = d2;
// Regs roll around if r3 is less than r1.
- // Artifically increase r3 by 16 so we can calculate
+ // Artificially increase r3 by 16 so we can calculate
// the number of regs stored properly.
if (r3 < r1) r3 += 16;