diff options
| author | Refael Ackermann <refack@gmail.com> | 2019-05-28 08:46:21 -0400 |
|---|---|---|
| committer | Refael Ackermann <refack@gmail.com> | 2019-06-01 09:55:12 -0400 |
| commit | ed74896b1fae1c163b3906163f3bf46326618ddb (patch) | |
| tree | 7fb05c5a19808e0c5cd95837528e9005999cf540 /deps/v8/src/wasm/baseline/mips64 | |
| parent | 2a850cd0664a4eee51f44d0bb8c2f7a3fe444154 (diff) | |
| download | node-new-ed74896b1fae1c163b3906163f3bf46326618ddb.tar.gz | |
deps: update V8 to 7.5.288.22
PR-URL: https://github.com/nodejs/node/pull/27375
Reviewed-By: Michaël Zasso <targos@protonmail.com>
Reviewed-By: Ujjwal Sharma <usharma1998@gmail.com>
Reviewed-By: Refael Ackermann <refack@gmail.com>
Reviewed-By: Matteo Collina <matteo.collina@gmail.com>
Reviewed-By: Colin Ihrig <cjihrig@gmail.com>
Reviewed-By: Rich Trott <rtrott@gmail.com>
Diffstat (limited to 'deps/v8/src/wasm/baseline/mips64')
| -rw-r--r-- | deps/v8/src/wasm/baseline/mips64/OWNERS | 4 | ||||
| -rw-r--r-- | deps/v8/src/wasm/baseline/mips64/liftoff-assembler-mips64.h | 9 |
2 files changed, 10 insertions, 3 deletions
diff --git a/deps/v8/src/wasm/baseline/mips64/OWNERS b/deps/v8/src/wasm/baseline/mips64/OWNERS index b455d9ef29..cab3679d65 100644 --- a/deps/v8/src/wasm/baseline/mips64/OWNERS +++ b/deps/v8/src/wasm/baseline/mips64/OWNERS @@ -1,3 +1 @@ -arikalo@wavecomp.com -prudic@wavecomp.com -skovacevic@wavecomp.com +xwafish@gmail.com diff --git a/deps/v8/src/wasm/baseline/mips64/liftoff-assembler-mips64.h b/deps/v8/src/wasm/baseline/mips64/liftoff-assembler-mips64.h index 3a963cefd6..7bfa172def 100644 --- a/deps/v8/src/wasm/baseline/mips64/liftoff-assembler-mips64.h +++ b/deps/v8/src/wasm/baseline/mips64/liftoff-assembler-mips64.h @@ -500,6 +500,10 @@ void LiftoffAssembler::FillI64Half(Register, uint32_t index, RegPairHalf) { UNREACHABLE(); } +void LiftoffAssembler::emit_i32_add(Register dst, Register lhs, int32_t imm) { + Addu(dst, lhs, Operand(imm)); +} + void LiftoffAssembler::emit_i32_mul(Register dst, Register lhs, Register rhs) { TurboAssembler::Mul(dst, lhs, rhs); } @@ -590,6 +594,11 @@ I32_SHIFTOP_I(shr, srl) #undef I32_SHIFTOP #undef I32_SHIFTOP_I +void LiftoffAssembler::emit_i64_add(LiftoffRegister dst, LiftoffRegister lhs, + int32_t imm) { + Daddu(dst.gp(), lhs.gp(), Operand(imm)); +} + void LiftoffAssembler::emit_i64_mul(LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { TurboAssembler::Dmul(dst.gp(), lhs.gp(), rhs.gp()); |