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author | Michaël Zasso <targos@protonmail.com> | 2016-12-23 16:30:57 +0100 |
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committer | Michaël Zasso <targos@protonmail.com> | 2017-01-26 22:46:17 +0100 |
commit | 2739185b790e040c3b044c577327f5d44bffad4a (patch) | |
tree | 29a466999212f4c85958379d9d400eec8a185ba5 /deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc | |
parent | a67a04d7654faaa04c8da00e42981ebc9fd0911c (diff) | |
download | node-new-2739185b790e040c3b044c577327f5d44bffad4a.tar.gz |
deps: update V8 to 5.5.372.40
PR-URL: https://github.com/nodejs/node/pull/9618
Reviewed-By: Ali Ijaz Sheikh <ofrobots@google.com>
Reviewed-By: Ben Noordhuis <info@bnoordhuis.nl>
Diffstat (limited to 'deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc')
-rw-r--r-- | deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc | 242 |
1 files changed, 242 insertions, 0 deletions
diff --git a/deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc b/deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc index c82cb9fe4f..be77126688 100644 --- a/deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc +++ b/deps/v8/test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc @@ -719,6 +719,51 @@ TEST_F(InstructionSelectorTest, Word64ShlWithWord64And) { } } +TEST_F(InstructionSelectorTest, Word32SarWithWord32Shl) { + { + StreamBuilder m(this, MachineType::Int32(), MachineType::Int32()); + Node* const p0 = m.Parameter(0); + Node* const r = + m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(24)), m.Int32Constant(24)); + m.Return(r); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + EXPECT_EQ(kMips64Seb, s[0]->arch_opcode()); + ASSERT_EQ(1U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + ASSERT_EQ(1U, s[0]->OutputCount()); + EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output())); + } + { + StreamBuilder m(this, MachineType::Int32(), MachineType::Int32()); + Node* const p0 = m.Parameter(0); + Node* const r = + m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(16)), m.Int32Constant(16)); + m.Return(r); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + EXPECT_EQ(kMips64Seh, s[0]->arch_opcode()); + ASSERT_EQ(1U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + ASSERT_EQ(1U, s[0]->OutputCount()); + EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output())); + } + { + StreamBuilder m(this, MachineType::Int32(), MachineType::Int32()); + Node* const p0 = m.Parameter(0); + Node* const r = + m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(32)), m.Int32Constant(32)); + m.Return(r); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + EXPECT_EQ(kMips64Shl, s[0]->arch_opcode()); + ASSERT_EQ(2U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(1))); + ASSERT_EQ(1U, s[0]->OutputCount()); + EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output())); + } +} // ---------------------------------------------------------------------------- // MUL/DIV instructions. @@ -1491,6 +1536,203 @@ TEST_F(InstructionSelectorTest, Float64Abs) { EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); } +TEST_F(InstructionSelectorTest, Float32AddWithFloat32Mul) { + { + StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), + MachineType::Float32(), MachineType::Float32()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* const n = m.Float32Add(m.Float32Mul(p0, p1), p2); + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MaddS, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MaddfS, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); + } + { + StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), + MachineType::Float32(), MachineType::Float32()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* const n = m.Float32Add(p0, m.Float32Mul(p1, p2)); + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MaddS, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MaddfS, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); + } +} + +TEST_F(InstructionSelectorTest, Float64AddWithFloat64Mul) { + { + StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), + MachineType::Float64(), MachineType::Float64()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* const n = m.Float64Add(m.Float64Mul(p0, p1), p2); + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MaddD, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MaddfD, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); + } + { + StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), + MachineType::Float64(), MachineType::Float64()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* const n = m.Float64Add(p0, m.Float64Mul(p1, p2)); + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MaddD, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MaddfD, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); + } +} + +TEST_F(InstructionSelectorTest, Float32SubWithFloat32Mul) { + StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(), + MachineType::Float32(), MachineType::Float32()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* n; + if (kArchVariant == kMips64r2) { + n = m.Float32Sub(m.Float32Mul(p1, p2), p0); + } else if (kArchVariant == kMips64r6) { + n = m.Float32Sub(p0, m.Float32Mul(p1, p2)); + } + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MsubS, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MsubfS, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); +} + +TEST_F(InstructionSelectorTest, Float64SubWithFloat64Mul) { + StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), + MachineType::Float64(), MachineType::Float64()); + Node* const p0 = m.Parameter(0); + Node* const p1 = m.Parameter(1); + Node* const p2 = m.Parameter(2); + Node* n; + if (kArchVariant == kMips64r2) { + n = m.Float64Sub(m.Float64Mul(p1, p2), p0); + } else if (kArchVariant == kMips64r6) { + n = m.Float64Sub(p0, m.Float64Mul(p1, p2)); + } + m.Return(n); + Stream s = m.Build(); + ASSERT_EQ(1U, s.size()); + if (kArchVariant == kMips64r2) { + EXPECT_EQ(kMips64MsubD, s[0]->arch_opcode()); + } else if (kArchVariant == kMips64r6) { + EXPECT_EQ(kMips64MsubfD, s[0]->arch_opcode()); + } + ASSERT_EQ(3U, s[0]->InputCount()); + EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); + EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); + EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2))); + ASSERT_EQ(1U, s[0]->OutputCount()); + if (kArchVariant == kMips64r2) { + EXPECT_FALSE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } else if (kArchVariant == kMips64r6) { + EXPECT_TRUE( + UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy()); + } + EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); + EXPECT_EQ(kFlags_none, s[0]->flags_mode()); +} TEST_F(InstructionSelectorTest, Float64Max) { StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), |