diff options
Diffstat (limited to 'deps/v8/src/arm/simulator-arm.cc')
| -rw-r--r-- | deps/v8/src/arm/simulator-arm.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/deps/v8/src/arm/simulator-arm.cc b/deps/v8/src/arm/simulator-arm.cc index 9dc417bb71..f3927720fb 100644 --- a/deps/v8/src/arm/simulator-arm.cc +++ b/deps/v8/src/arm/simulator-arm.cc @@ -1893,14 +1893,14 @@ void Simulator::DecodeUnconditional(Instr* instr) { // void Simulator::DecodeTypeVFP(Instr* instr) // The Following ARMv7 VFPv instructions are currently supported. -// fmsr :Sn = Rt -// fmrs :Rt = Sn -// fsitod: Dd = Sm -// ftosid: Sd = Dm -// Dd = faddd(Dn, Dm) -// Dd = fsubd(Dn, Dm) -// Dd = fmuld(Dn, Dm) -// Dd = fdivd(Dn, Dm) +// vmov :Sn = Rt +// vmov :Rt = Sn +// vcvt: Dd = Sm +// vcvt: Sd = Dm +// Dd = vadd(Dn, Dm) +// Dd = vsub(Dn, Dm) +// Dd = vmul(Dn, Dm) +// Dd = vdiv(Dn, Dm) // vcmp(Dd, Dm) // VMRS void Simulator::DecodeTypeVFP(Instr* instr) { @@ -2020,8 +2020,8 @@ void Simulator::DecodeTypeVFP(Instr* instr) { // void Simulator::DecodeType6CoprocessorIns(Instr* instr) // Decode Type 6 coprocessor instructions. -// Dm = fmdrr(Rt, Rt2) -// <Rt, Rt2> = fmrrd(Dm) +// Dm = vmov(Rt, Rt2) +// <Rt, Rt2> = vmov(Dm) void Simulator::DecodeType6CoprocessorIns(Instr* instr) { ASSERT((instr->TypeField() == 6)); |