diff options
Diffstat (limited to 'deps/v8/src/codegen/mips')
| -rw-r--r-- | deps/v8/src/codegen/mips/constants-mips.h | 15 | ||||
| -rw-r--r-- | deps/v8/src/codegen/mips/interface-descriptors-mips.cc | 27 | ||||
| -rw-r--r-- | deps/v8/src/codegen/mips/macro-assembler-mips.cc | 54 | ||||
| -rw-r--r-- | deps/v8/src/codegen/mips/macro-assembler-mips.h | 14 |
4 files changed, 75 insertions, 35 deletions
diff --git a/deps/v8/src/codegen/mips/constants-mips.h b/deps/v8/src/codegen/mips/constants-mips.h index d2b3f6b08f..67d12155a3 100644 --- a/deps/v8/src/codegen/mips/constants-mips.h +++ b/deps/v8/src/codegen/mips/constants-mips.h @@ -89,15 +89,18 @@ const uint32_t kHoleNanLower32Offset = 4; #error Unknown endianness #endif -#define IsFp64Mode() (kFpuMode == kFP64) -#define IsFp32Mode() (kFpuMode == kFP32) -#define IsFpxxMode() (kFpuMode == kFPXX) +constexpr bool IsFp64Mode() { return kFpuMode == kFP64; } +constexpr bool IsFp32Mode() { return kFpuMode == kFP32; } +constexpr bool IsFpxxMode() { return kFpuMode == kFPXX; } #ifndef _MIPS_ARCH_MIPS32RX -#define IsMipsArchVariant(check) (kArchVariant == check) +constexpr bool IsMipsArchVariant(const ArchVariants check) { + return kArchVariant == check; +} #else -#define IsMipsArchVariant(check) \ - (CpuFeatures::IsSupported(static_cast<CpuFeature>(check))) +bool IsMipsArchVariant(const ArchVariants check) { + return CpuFeatures::IsSupported(static_cast<CpuFeature>(check)); +} #endif #if defined(V8_TARGET_LITTLE_ENDIAN) diff --git a/deps/v8/src/codegen/mips/interface-descriptors-mips.cc b/deps/v8/src/codegen/mips/interface-descriptors-mips.cc index 0a36e26577..8b8bc1b56d 100644 --- a/deps/v8/src/codegen/mips/interface-descriptors-mips.cc +++ b/deps/v8/src/codegen/mips/interface-descriptors-mips.cc @@ -31,19 +31,34 @@ bool CallInterfaceDescriptor::IsValidFloatParameterRegister(Register reg) { return reg.code() % 2 == 0; } -void WasmI32AtomicWaitDescriptor::InitializePlatformSpecific( +void WasmI32AtomicWait32Descriptor::InitializePlatformSpecific( CallInterfaceDescriptorData* data) { - /* Register t4 correspond to f12 FPU register. */ - const Register default_stub_registers[] = {a0, a1, t4}; + const Register default_stub_registers[] = {a0, a1, a2, a3}; CHECK_EQ(static_cast<size_t>(kParameterCount), arraysize(default_stub_registers)); data->InitializePlatformSpecific(kParameterCount, default_stub_registers); } -void WasmI64AtomicWaitDescriptor::InitializePlatformSpecific( +void WasmI32AtomicWait64Descriptor::InitializePlatformSpecific( CallInterfaceDescriptorData* data) { - /* Register t4 correspond to f12 FPU register. */ - const Register default_stub_registers[] = {a0, a1, a2, t4}; + const Register default_stub_registers[] = {a0, a1, a2}; + CHECK_EQ(static_cast<size_t>(kParameterCount), + arraysize(default_stub_registers)); + data->InitializePlatformSpecific(kParameterCount, default_stub_registers); +} + +void WasmI64AtomicWait32Descriptor::InitializePlatformSpecific( + CallInterfaceDescriptorData* data) { + const Register default_stub_registers[] = {a0, a1, a2, a3, t0}; + CHECK_EQ(static_cast<size_t>(kParameterCount - kStackArgumentsCount), + arraysize(default_stub_registers)); + data->InitializePlatformSpecific(kParameterCount - kStackArgumentsCount, + default_stub_registers); +} + +void WasmI64AtomicWait64Descriptor::InitializePlatformSpecific( + CallInterfaceDescriptorData* data) { + const Register default_stub_registers[] = {a0, a1, a2}; CHECK_EQ(static_cast<size_t>(kParameterCount), arraysize(default_stub_registers)); data->InitializePlatformSpecific(kParameterCount, default_stub_registers); diff --git a/deps/v8/src/codegen/mips/macro-assembler-mips.cc b/deps/v8/src/codegen/mips/macro-assembler-mips.cc index 6526f48da5..6ae70798c1 100644 --- a/deps/v8/src/codegen/mips/macro-assembler-mips.cc +++ b/deps/v8/src/codegen/mips/macro-assembler-mips.cc @@ -4668,6 +4668,7 @@ void MacroAssembler::DecrementCounter(StatsCounter* counter, int value, // Debugging. void TurboAssembler::Trap() { stop(); } +void TurboAssembler::DebugBreak() { stop(); } void TurboAssembler::Assert(Condition cc, AbortReason reason, Register rs, Operand rt) { @@ -5374,31 +5375,38 @@ void TurboAssembler::CallCFunctionHelper(Register function_base, // Save the frame pointer and PC so that the stack layout remains iterable, // even without an ExitFrame which normally exists between JS and C frames. - if (isolate() != nullptr) { - // 't' registers are caller-saved so this is safe as a scratch register. - Register scratch1 = t4; - Register scratch2 = t5; - DCHECK(!AreAliased(scratch1, scratch2, function_base)); - - Label get_pc; - mov(scratch1, ra); - Call(&get_pc); - - bind(&get_pc); - mov(scratch2, ra); - mov(ra, scratch1); - - li(scratch1, ExternalReference::fast_c_call_caller_pc_address(isolate())); - sw(scratch2, MemOperand(scratch1)); - li(scratch1, ExternalReference::fast_c_call_caller_fp_address(isolate())); - sw(fp, MemOperand(scratch1)); + // 't' registers are caller-saved so this is safe as a scratch register. + Register pc_scratch = t4; + Register scratch = t5; + DCHECK(!AreAliased(pc_scratch, scratch, function_base)); + + mov(scratch, ra); + nal(); + mov(pc_scratch, ra); + mov(ra, scratch); + + // See x64 code for reasoning about how to address the isolate data fields. + if (root_array_available()) { + sw(pc_scratch, MemOperand(kRootRegister, + IsolateData::fast_c_call_caller_pc_offset())); + sw(fp, MemOperand(kRootRegister, + IsolateData::fast_c_call_caller_fp_offset())); + } else { + DCHECK_NOT_NULL(isolate()); + li(scratch, ExternalReference::fast_c_call_caller_pc_address(isolate())); + sw(pc_scratch, MemOperand(scratch)); + li(scratch, ExternalReference::fast_c_call_caller_fp_address(isolate())); + sw(fp, MemOperand(scratch)); } Call(function_base, function_offset); - if (isolate() != nullptr) { - // We don't unset the PC; the FP is the source of truth. - Register scratch = t4; + // We don't unset the PC; the FP is the source of truth. + if (root_array_available()) { + sw(zero_reg, MemOperand(kRootRegister, + IsolateData::fast_c_call_caller_fp_offset())); + } else { + DCHECK_NOT_NULL(isolate()); li(scratch, ExternalReference::fast_c_call_caller_fp_address(isolate())); sw(zero_reg, MemOperand(scratch)); } @@ -5469,7 +5477,9 @@ void TurboAssembler::ResetSpeculationPoisonRegister() { li(kSpeculationPoisonRegister, -1); } -void TurboAssembler::CallForDeoptimization(Address target, int deopt_id) { +void TurboAssembler::CallForDeoptimization(Address target, int deopt_id, + Label* exit, DeoptimizeKind kind) { + USE(exit, kind); NoRootArrayScope no_root_array(this); // Save the deipt id in kRootRegister (we don't need the roots array from now diff --git a/deps/v8/src/codegen/mips/macro-assembler-mips.h b/deps/v8/src/codegen/mips/macro-assembler-mips.h index f916b9d101..d7441c2fcf 100644 --- a/deps/v8/src/codegen/mips/macro-assembler-mips.h +++ b/deps/v8/src/codegen/mips/macro-assembler-mips.h @@ -103,6 +103,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { // Debugging. void Trap() override; + void DebugBreak() override; // Calls Abort(msg) if the condition cc is not satisfied. // Use --debug_code to enable. @@ -236,7 +237,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { // The return address on the stack is used by frame iteration. void StoreReturnAddressAndCall(Register target); - void CallForDeoptimization(Address target, int deopt_id); + void CallForDeoptimization(Address target, int deopt_id, Label* exit, + DeoptimizeKind kind); void Ret(COND_ARGS); inline void Ret(BranchDelaySlot bd, Condition cond = al, @@ -813,6 +815,16 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { void ResetSpeculationPoisonRegister(); + // Control-flow integrity: + + // Define a function entrypoint. This doesn't emit any code for this + // architecture, as control-flow integrity is not supported for it. + void CodeEntry() {} + // Define an exception handler. + void ExceptionHandler() {} + // Define an exception handler and bind a label. + void BindExceptionHandler(Label* label) { bind(label); } + protected: void BranchLong(Label* L, BranchDelaySlot bdslot); |