1 files changed, 8 insertions, 0 deletions
diff --git a/deps/v8/src/codegen/riscv/base-riscv-i.cc b/deps/v8/src/codegen/riscv/base-riscv-i.cc
index 19687c9370..a3d7029248 100644
--- a/deps/v8/src/codegen/riscv/base-riscv-i.cc
+++ b/deps/v8/src/codegen/riscv/base-riscv-i.cc
@@ -18,11 +18,13 @@ void AssemblerRISCVI::auipc(Register rd, int32_t imm20) {
 
 void AssemblerRISCVI::jal(Register rd, int32_t imm21) {
   GenInstrJ(JAL, rd, imm21);
+  ClearVectorunit();
   BlockTrampolinePoolFor(1);
 }
 
 void AssemblerRISCVI::jalr(Register rd, Register rs1, int16_t imm12) {
   GenInstrI(0b000, JALR, rd, rs1, imm12);
+  ClearVectorunit();
   BlockTrampolinePoolFor(1);
 }
 
@@ -30,26 +32,32 @@ void AssemblerRISCVI::jalr(Register rd, Register rs1, int16_t imm12) {
 
 void AssemblerRISCVI::beq(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b000, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 void AssemblerRISCVI::bne(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b001, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 void AssemblerRISCVI::blt(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b100, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 void AssemblerRISCVI::bge(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b101, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 void AssemblerRISCVI::bltu(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b110, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 void AssemblerRISCVI::bgeu(Register rs1, Register rs2, int16_t imm13) {
   GenInstrBranchCC_rri(0b111, rs1, rs2, imm13);
+  ClearVectorunit();
 }
 
 // Loads