diff options
Diffstat (limited to 'deps/v8/src/compiler/ia32/instruction-selector-ia32.cc')
-rw-r--r-- | deps/v8/src/compiler/ia32/instruction-selector-ia32.cc | 94 |
1 files changed, 72 insertions, 22 deletions
diff --git a/deps/v8/src/compiler/ia32/instruction-selector-ia32.cc b/deps/v8/src/compiler/ia32/instruction-selector-ia32.cc index c827c68a5f..5548f55a1e 100644 --- a/deps/v8/src/compiler/ia32/instruction-selector-ia32.cc +++ b/deps/v8/src/compiler/ia32/instruction-selector-ia32.cc @@ -351,6 +351,11 @@ void InstructionSelector::VisitStore(Node* node) { } } +void InstructionSelector::VisitProtectedStore(Node* node) { + // TODO(eholk) + UNIMPLEMENTED(); +} + // Architecture supports unaligned access, therefore VisitLoad is used instead void InstructionSelector::VisitUnalignedLoad(Node* node) { UNREACHABLE(); } @@ -1203,10 +1208,13 @@ void VisitCompareWithMemoryOperand(InstructionSelector* selector, } else if (cont->IsDeoptimize()) { selector->EmitDeoptimize(opcode, 0, nullptr, input_count, inputs, cont->reason(), cont->frame_state()); - } else { - DCHECK(cont->IsSet()); + } else if (cont->IsSet()) { InstructionOperand output = g.DefineAsRegister(cont->result()); selector->Emit(opcode, 1, &output, input_count, inputs); + } else { + DCHECK(cont->IsTrap()); + inputs[input_count++] = g.UseImmediate(cont->trap_id()); + selector->Emit(opcode, 0, nullptr, input_count, inputs); } } @@ -1222,9 +1230,12 @@ void VisitCompare(InstructionSelector* selector, InstructionCode opcode, } else if (cont->IsDeoptimize()) { selector->EmitDeoptimize(opcode, g.NoOutput(), left, right, cont->reason(), cont->frame_state()); - } else { - DCHECK(cont->IsSet()); + } else if (cont->IsSet()) { selector->Emit(opcode, g.DefineAsByteRegister(cont->result()), left, right); + } else { + DCHECK(cont->IsTrap()); + selector->Emit(opcode, g.NoOutput(), left, right, + g.UseImmediate(cont->trap_id())); } } @@ -1240,21 +1251,54 @@ void VisitCompare(InstructionSelector* selector, InstructionCode opcode, VisitCompare(selector, opcode, g.UseRegister(left), g.Use(right), cont); } +MachineType MachineTypeForNarrow(Node* node, Node* hint_node) { + if (hint_node->opcode() == IrOpcode::kLoad) { + MachineType hint = LoadRepresentationOf(hint_node->op()); + if (node->opcode() == IrOpcode::kInt32Constant || + node->opcode() == IrOpcode::kInt64Constant) { + int64_t constant = node->opcode() == IrOpcode::kInt32Constant + ? OpParameter<int32_t>(node) + : OpParameter<int64_t>(node); + if (hint == MachineType::Int8()) { + if (constant >= std::numeric_limits<int8_t>::min() && + constant <= std::numeric_limits<int8_t>::max()) { + return hint; + } + } else if (hint == MachineType::Uint8()) { + if (constant >= std::numeric_limits<uint8_t>::min() && + constant <= std::numeric_limits<uint8_t>::max()) { + return hint; + } + } else if (hint == MachineType::Int16()) { + if (constant >= std::numeric_limits<int16_t>::min() && + constant <= std::numeric_limits<int16_t>::max()) { + return hint; + } + } else if (hint == MachineType::Uint16()) { + if (constant >= std::numeric_limits<uint16_t>::min() && + constant <= std::numeric_limits<uint16_t>::max()) { + return hint; + } + } else if (hint == MachineType::Int32()) { + return hint; + } else if (hint == MachineType::Uint32()) { + if (constant >= 0) return hint; + } + } + } + return node->opcode() == IrOpcode::kLoad ? LoadRepresentationOf(node->op()) + : MachineType::None(); +} + // Tries to match the size of the given opcode to that of the operands, if // possible. InstructionCode TryNarrowOpcodeSize(InstructionCode opcode, Node* left, Node* right, FlagsContinuation* cont) { - // Currently, if one of the two operands is not a Load, we don't know what its - // machine representation is, so we bail out. - // TODO(epertoso): we can probably get some size information out of immediates - // and phi nodes. - if (left->opcode() != IrOpcode::kLoad || right->opcode() != IrOpcode::kLoad) { - return opcode; - } + // TODO(epertoso): we can probably get some size information out of phi nodes. // If the load representations don't match, both operands will be // zero/sign-extended to 32bit. - MachineType left_type = LoadRepresentationOf(left->op()); - MachineType right_type = LoadRepresentationOf(right->op()); + MachineType left_type = MachineTypeForNarrow(left, right); + MachineType right_type = MachineTypeForNarrow(right, left); if (left_type == right_type) { switch (left_type.representation()) { case MachineRepresentation::kBit: @@ -1332,10 +1376,8 @@ void VisitWordCompare(InstructionSelector* selector, Node* node, // Match immediates on right side of comparison. if (g.CanBeImmediate(right)) { - if (g.CanBeMemoryOperand(opcode, node, left, effect_level)) { - // TODO(epertoso): we should use `narrowed_opcode' here once we match - // immediates too. - return VisitCompareWithMemoryOperand(selector, opcode, left, + if (g.CanBeMemoryOperand(narrowed_opcode, node, left, effect_level)) { + return VisitCompareWithMemoryOperand(selector, narrowed_opcode, left, g.UseImmediate(right), cont); } return VisitCompare(selector, opcode, g.Use(left), g.UseImmediate(right), @@ -1352,11 +1394,6 @@ void VisitWordCompare(InstructionSelector* selector, Node* node, cont); } - if (g.CanBeBetterLeftOperand(right)) { - if (!node->op()->HasProperty(Operator::kCommutative)) cont->Commute(); - std::swap(left, right); - } - return VisitCompare(selector, opcode, left, right, cont, node->op()->HasProperty(Operator::kCommutative)); } @@ -1501,6 +1538,19 @@ void InstructionSelector::VisitDeoptimizeUnless(Node* node) { VisitWordCompareZero(this, node, node->InputAt(0), &cont); } +void InstructionSelector::VisitTrapIf(Node* node, Runtime::FunctionId func_id) { + FlagsContinuation cont = + FlagsContinuation::ForTrap(kNotEqual, func_id, node->InputAt(1)); + VisitWordCompareZero(this, node, node->InputAt(0), &cont); +} + +void InstructionSelector::VisitTrapUnless(Node* node, + Runtime::FunctionId func_id) { + FlagsContinuation cont = + FlagsContinuation::ForTrap(kEqual, func_id, node->InputAt(1)); + VisitWordCompareZero(this, node, node->InputAt(0), &cont); +} + void InstructionSelector::VisitSwitch(Node* node, const SwitchInfo& sw) { IA32OperandGenerator g(this); InstructionOperand value_operand = g.UseRegister(node->InputAt(0)); |