diff options
Diffstat (limited to 'deps/v8/src/compiler/x64/instruction-selector-x64.cc')
| -rw-r--r-- | deps/v8/src/compiler/x64/instruction-selector-x64.cc | 97 |
1 files changed, 83 insertions, 14 deletions
diff --git a/deps/v8/src/compiler/x64/instruction-selector-x64.cc b/deps/v8/src/compiler/x64/instruction-selector-x64.cc index 89dc956318..3f4e2b3b1c 100644 --- a/deps/v8/src/compiler/x64/instruction-selector-x64.cc +++ b/deps/v8/src/compiler/x64/instruction-selector-x64.cc @@ -26,7 +26,8 @@ class X64OperandGenerator final : public OperandGenerator { return true; case IrOpcode::kInt64Constant: { const int64_t value = OpParameter<int64_t>(node); - return value == static_cast<int64_t>(static_cast<int32_t>(value)); + return std::numeric_limits<int32_t>::min() < value && + value <= std::numeric_limits<int32_t>::max(); } case IrOpcode::kNumberConstant: { const double value = OpParameter<double>(node); @@ -230,6 +231,8 @@ ArchOpcode GetLoadOpcode(LoadRepresentation load_rep) { opcode = kX64Movq; break; case MachineRepresentation::kSimd128: // Fall through. + opcode = kX64Movdqu; + break; case MachineRepresentation::kSimd1x4: // Fall through. case MachineRepresentation::kSimd1x8: // Fall through. case MachineRepresentation::kSimd1x16: // Fall through. @@ -265,6 +268,8 @@ ArchOpcode GetStoreOpcode(StoreRepresentation store_rep) { return kX64Movq; break; case MachineRepresentation::kSimd128: // Fall through. + return kX64Movdqu; + break; case MachineRepresentation::kSimd1x4: // Fall through. case MachineRepresentation::kSimd1x8: // Fall through. case MachineRepresentation::kSimd1x16: // Fall through. @@ -278,6 +283,15 @@ ArchOpcode GetStoreOpcode(StoreRepresentation store_rep) { } // namespace +void InstructionSelector::VisitStackSlot(Node* node) { + StackSlotRepresentation rep = StackSlotRepresentationOf(node->op()); + int slot = frame_->AllocateSpillSlot(rep.size()); + OperandGenerator g(this); + + Emit(kArchStackSlot, g.DefineAsRegister(node), + sequence()->AddImmediate(Constant(slot)), 0, nullptr); +} + void InstructionSelector::VisitLoad(Node* node) { LoadRepresentation load_rep = LoadRepresentationOf(node->op()); X64OperandGenerator g(this); @@ -2438,7 +2452,15 @@ VISIT_ATOMIC_BINOP(Or) VISIT_ATOMIC_BINOP(Xor) #undef VISIT_ATOMIC_BINOP -#define SIMD_TYPES(V) V(I32x4) +#define SIMD_TYPES(V) \ + V(I32x4) \ + V(I16x8) \ + V(I8x16) + +#define SIMD_FORMAT_LIST(V) \ + V(32x4) \ + V(16x8) \ + V(8x16) #define SIMD_ZERO_OP_LIST(V) \ V(S128Zero) \ @@ -2446,13 +2468,9 @@ VISIT_ATOMIC_BINOP(Xor) V(S1x8Zero) \ V(S1x16Zero) -#define SIMD_SHIFT_OPCODES(V) \ - V(I32x4Shl) \ - V(I32x4ShrS) \ - V(I32x4ShrU) - #define SIMD_BINOP_LIST(V) \ V(I32x4Add) \ + V(I32x4AddHoriz) \ V(I32x4Sub) \ V(I32x4Mul) \ V(I32x4MinS) \ @@ -2460,7 +2478,46 @@ VISIT_ATOMIC_BINOP(Xor) V(I32x4Eq) \ V(I32x4Ne) \ V(I32x4MinU) \ - V(I32x4MaxU) + V(I32x4MaxU) \ + V(I16x8Add) \ + V(I16x8AddSaturateS) \ + V(I16x8AddHoriz) \ + V(I16x8Sub) \ + V(I16x8SubSaturateS) \ + V(I16x8Mul) \ + V(I16x8MinS) \ + V(I16x8MaxS) \ + V(I16x8Eq) \ + V(I16x8Ne) \ + V(I16x8AddSaturateU) \ + V(I16x8SubSaturateU) \ + V(I16x8MinU) \ + V(I16x8MaxU) \ + V(I8x16Add) \ + V(I8x16AddSaturateS) \ + V(I8x16Sub) \ + V(I8x16SubSaturateS) \ + V(I8x16MinS) \ + V(I8x16MaxS) \ + V(I8x16Eq) \ + V(I8x16Ne) \ + V(I8x16AddSaturateU) \ + V(I8x16SubSaturateU) \ + V(I8x16MinU) \ + V(I8x16MaxU) \ + V(S128And) \ + V(S128Or) \ + V(S128Xor) + +#define SIMD_UNOP_LIST(V) V(S128Not) + +#define SIMD_SHIFT_OPCODES(V) \ + V(I32x4Shl) \ + V(I32x4ShrS) \ + V(I32x4ShrU) \ + V(I16x8Shl) \ + V(I16x8ShrS) \ + V(I16x8ShrU) #define VISIT_SIMD_SPLAT(Type) \ void InstructionSelector::Visit##Type##Splat(Node* node) { \ @@ -2510,6 +2567,15 @@ SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP) SIMD_SHIFT_OPCODES(VISIT_SIMD_SHIFT) #undef VISIT_SIMD_SHIFT +#define VISIT_SIMD_UNOP(Opcode) \ + void InstructionSelector::Visit##Opcode(Node* node) { \ + X64OperandGenerator g(this); \ + Emit(kX64##Opcode, g.DefineAsRegister(node), \ + g.UseRegister(node->InputAt(0))); \ + } +SIMD_UNOP_LIST(VISIT_SIMD_UNOP) +#undef VISIT_SIMD_UNOP + #define VISIT_SIMD_BINOP(Opcode) \ void InstructionSelector::Visit##Opcode(Node* node) { \ X64OperandGenerator g(this); \ @@ -2519,12 +2585,15 @@ SIMD_SHIFT_OPCODES(VISIT_SIMD_SHIFT) SIMD_BINOP_LIST(VISIT_SIMD_BINOP) #undef VISIT_SIMD_BINOP -void InstructionSelector::VisitS32x4Select(Node* node) { - X64OperandGenerator g(this); - Emit(kX64S32x4Select, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), - g.UseRegister(node->InputAt(2))); -} +#define SIMD_VISIT_SELECT_OP(format) \ + void InstructionSelector::VisitS##format##Select(Node* node) { \ + X64OperandGenerator g(this); \ + Emit(kX64S128Select, g.DefineSameAsFirst(node), \ + g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \ + g.UseRegister(node->InputAt(2))); \ + } +SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP) +#undef SIMD_VISIT_SELECT_OP void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) { UNREACHABLE(); |