diff options
Diffstat (limited to 'deps/v8/src/mips/assembler-mips.cc')
-rw-r--r-- | deps/v8/src/mips/assembler-mips.cc | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/deps/v8/src/mips/assembler-mips.cc b/deps/v8/src/mips/assembler-mips.cc index a8b6cc7c32..e50a239a4a 100644 --- a/deps/v8/src/mips/assembler-mips.cc +++ b/deps/v8/src/mips/assembler-mips.cc @@ -285,10 +285,7 @@ Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) void Assembler::GetCode(CodeDesc* desc) { - if (IsPrevInstrCompactBranch()) { - nop(); - ClearCompactBranchState(); - } + EmitForbiddenSlotInstruction(); DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap. // Set up code descriptor. desc->buffer = buffer_; @@ -302,10 +299,7 @@ void Assembler::GetCode(CodeDesc* desc) { void Assembler::Align(int m) { DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m)); - if (IsPrevInstrCompactBranch()) { - nop(); - ClearCompactBranchState(); - } + EmitForbiddenSlotInstruction(); while ((pc_offset() & (m - 1)) != 0) { nop(); } @@ -2092,33 +2086,36 @@ void Assembler::ldc1(FPURegister fd, const MemOperand& src) { // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit // load to two 32-bit loads. DCHECK(!src.rm().is(at)); - if (IsFp64Mode()) { + if (IsFp32Mode()) { // fp32 mode. if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) { GenInstrImmediate(LWC1, src.rm(), fd, src.offset_ + Register::kMantissaOffset); - GenInstrImmediate(LW, src.rm(), at, + FPURegister nextfpreg; + nextfpreg.setcode(fd.code() + 1); + GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + Register::kExponentOffset); - mthc1(at, fd); } else { // Offset > 16 bits, use multiple instructions to load. LoadRegPlusOffsetToAt(src); GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset); - GenInstrImmediate(LW, at, at, Register::kExponentOffset); - mthc1(at, fd); + FPURegister nextfpreg; + nextfpreg.setcode(fd.code() + 1); + GenInstrImmediate(LWC1, at, nextfpreg, Register::kExponentOffset); } - } else { // fp32 mode. + } else { + DCHECK(IsFp64Mode() || IsFpxxMode()); + // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6 + DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) { GenInstrImmediate(LWC1, src.rm(), fd, src.offset_ + Register::kMantissaOffset); - FPURegister nextfpreg; - nextfpreg.setcode(fd.code() + 1); - GenInstrImmediate(LWC1, src.rm(), nextfpreg, + GenInstrImmediate(LW, src.rm(), at, src.offset_ + Register::kExponentOffset); + mthc1(at, fd); } else { // Offset > 16 bits, use multiple instructions to load. LoadRegPlusOffsetToAt(src); GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset); - FPURegister nextfpreg; - nextfpreg.setcode(fd.code() + 1); - GenInstrImmediate(LWC1, at, nextfpreg, Register::kExponentOffset); + GenInstrImmediate(LW, at, at, Register::kExponentOffset); + mthc1(at, fd); } } } @@ -2139,33 +2136,36 @@ void Assembler::sdc1(FPURegister fd, const MemOperand& src) { // store to two 32-bit stores. DCHECK(!src.rm().is(at)); DCHECK(!src.rm().is(t8)); - if (IsFp64Mode()) { + if (IsFp32Mode()) { // fp32 mode. if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) { GenInstrImmediate(SWC1, src.rm(), fd, src.offset_ + Register::kMantissaOffset); - mfhc1(at, fd); - GenInstrImmediate(SW, src.rm(), at, + FPURegister nextfpreg; + nextfpreg.setcode(fd.code() + 1); + GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + Register::kExponentOffset); } else { // Offset > 16 bits, use multiple instructions to load. LoadRegPlusOffsetToAt(src); GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset); - mfhc1(t8, fd); - GenInstrImmediate(SW, at, t8, Register::kExponentOffset); + FPURegister nextfpreg; + nextfpreg.setcode(fd.code() + 1); + GenInstrImmediate(SWC1, at, nextfpreg, Register::kExponentOffset); } - } else { // fp32 mode. + } else { + DCHECK(IsFp64Mode() || IsFpxxMode()); + // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6 + DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) { GenInstrImmediate(SWC1, src.rm(), fd, src.offset_ + Register::kMantissaOffset); - FPURegister nextfpreg; - nextfpreg.setcode(fd.code() + 1); - GenInstrImmediate(SWC1, src.rm(), nextfpreg, + mfhc1(at, fd); + GenInstrImmediate(SW, src.rm(), at, src.offset_ + Register::kExponentOffset); } else { // Offset > 16 bits, use multiple instructions to load. LoadRegPlusOffsetToAt(src); GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset); - FPURegister nextfpreg; - nextfpreg.setcode(fd.code() + 1); - GenInstrImmediate(SWC1, at, nextfpreg, Register::kExponentOffset); + mfhc1(t8, fd); + GenInstrImmediate(SW, at, t8, Register::kExponentOffset); } } } |