diff options
Diffstat (limited to 'deps/v8/src/mips/simulator-mips.h')
-rw-r--r-- | deps/v8/src/mips/simulator-mips.h | 80 |
1 files changed, 79 insertions, 1 deletions
diff --git a/deps/v8/src/mips/simulator-mips.h b/deps/v8/src/mips/simulator-mips.h index 1ed96bd003..40aba780ba 100644 --- a/deps/v8/src/mips/simulator-mips.h +++ b/deps/v8/src/mips/simulator-mips.h @@ -181,6 +181,43 @@ class Simulator { kNumFPURegisters }; + // MSA registers + enum MSARegister { + w0, + w1, + w2, + w3, + w4, + w5, + w6, + w7, + w8, + w9, + w10, + w11, + w12, + w13, + w14, + w15, + w16, + w17, + w18, + w19, + w20, + w21, + w22, + w23, + w24, + w25, + w26, + w27, + w28, + w29, + w30, + w31, + kNumMSARegisters + }; + explicit Simulator(Isolate* isolate); ~Simulator(); @@ -213,6 +250,10 @@ class Simulator { int32_t get_fpu_register_hi_word(int fpureg) const; float get_fpu_register_float(int fpureg) const; double get_fpu_register_double(int fpureg) const; + template <typename T> + void get_msa_register(int wreg, T* value); + template <typename T> + void set_msa_register(int wreg, const T* value); void set_fcsr_bit(uint32_t cc, bool value); bool test_fcsr_bit(uint32_t cc); void set_fcsr_rounding_mode(FPURoundingMode mode); @@ -293,6 +334,19 @@ class Simulator { // Helpers for data value tracing. enum TraceType { BYTE, HALF, WORD, DWORD, FLOAT, DOUBLE, FLOAT_DOUBLE }; + // MSA Data Format + enum MSADataFormat { MSA_VECT = 0, MSA_BYTE, MSA_HALF, MSA_WORD, MSA_DWORD }; + typedef union { + int8_t b[kMSALanesByte]; + uint8_t ub[kMSALanesByte]; + int16_t h[kMSALanesHalf]; + uint16_t uh[kMSALanesHalf]; + int32_t w[kMSALanesWord]; + uint32_t uw[kMSALanesWord]; + int64_t d[kMSALanesDword]; + uint64_t ud[kMSALanesDword]; + } msa_reg_t; + // Read and write memory. inline uint32_t ReadBU(int32_t addr); inline int32_t ReadB(int32_t addr); @@ -313,6 +367,10 @@ class Simulator { void TraceRegWr(int32_t value, TraceType t = WORD); void TraceRegWr(int64_t value, TraceType t = DWORD); + template <typename T> + void TraceMSARegWr(T* value, TraceType t); + template <typename T> + void TraceMSARegWr(T* value); void TraceMemWr(int32_t addr, int32_t value, TraceType t = WORD); void TraceMemRd(int32_t addr, int32_t value, TraceType t = WORD); void TraceMemWr(int32_t addr, int64_t value, TraceType t = DWORD); @@ -352,6 +410,21 @@ class Simulator { void DecodeTypeRegisterLRsType(); + int DecodeMsaDataFormat(); + void DecodeTypeMsaI8(); + void DecodeTypeMsaI5(); + void DecodeTypeMsaI10(); + void DecodeTypeMsaELM(); + void DecodeTypeMsaBIT(); + void DecodeTypeMsaMI10(); + void DecodeTypeMsa3R(); + void DecodeTypeMsa3RF(); + void DecodeTypeMsaVec(); + void DecodeTypeMsa2R(); + void DecodeTypeMsa2RF(); + template <typename T> + T MsaI5InstrHelper(uint32_t opcode, T ws, int32_t i5); + inline int32_t rs_reg() const { return instr_.RsValue(); } inline int32_t rs() const { return get_register(rs_reg()); } inline uint32_t rs_u() const { @@ -369,6 +442,9 @@ class Simulator { inline int32_t fd_reg() const { return instr_.FdValue(); } inline int32_t sa() const { return instr_.SaValue(); } inline int32_t lsa_sa() const { return instr_.LsaSaValue(); } + inline int32_t ws_reg() const { return instr_.WsValue(); } + inline int32_t wt_reg() const { return instr_.WtValue(); } + inline int32_t wd_reg() const { return instr_.WdValue(); } inline void SetResult(int32_t rd_reg, int32_t alu_out) { set_register(rd_reg, alu_out); @@ -480,7 +556,9 @@ class Simulator { // Coprocessor Registers. // Note: FP32 mode uses only the lower 32-bit part of each element, // the upper 32-bit is unpredictable. - int64_t FPUregisters_[kNumFPURegisters]; + // Note: FPUregisters_[] array is increased to 64 * 8B = 32 * 16B in + // order to support MSA registers + int64_t FPUregisters_[kNumFPURegisters * 2]; // FPU control register. uint32_t FCSR_; |