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Diffstat (limited to 'deps/v8/src/mips64/simulator-mips64.cc')
-rw-r--r--deps/v8/src/mips64/simulator-mips64.cc139
1 files changed, 86 insertions, 53 deletions
diff --git a/deps/v8/src/mips64/simulator-mips64.cc b/deps/v8/src/mips64/simulator-mips64.cc
index 7ec51b1cfe..320b97296a 100644
--- a/deps/v8/src/mips64/simulator-mips64.cc
+++ b/deps/v8/src/mips64/simulator-mips64.cc
@@ -949,6 +949,8 @@ void Simulator::TearDown(base::CustomMatcherHashMap* i_cache,
void* Simulator::RedirectExternalReference(Isolate* isolate,
void* external_function,
ExternalReference::Type type) {
+ base::LockGuard<base::Mutex> lock_guard(
+ isolate->simulator_redirection_mutex());
Redirection* redirection = Redirection::Get(isolate, external_function, type);
return redirection->address_of_swi_instruction();
}
@@ -1984,12 +1986,11 @@ void Simulator::Format(Instruction* instr, const char* format) {
// 64 bits of result. If they don't, the v1 result register contains a bogus
// value, which is fine because it is caller-saved.
-typedef ObjectPair (*SimulatorRuntimeCall)(int64_t arg0,
- int64_t arg1,
- int64_t arg2,
- int64_t arg3,
- int64_t arg4,
- int64_t arg5);
+typedef ObjectPair (*SimulatorRuntimeCall)(int64_t arg0, int64_t arg1,
+ int64_t arg2, int64_t arg3,
+ int64_t arg4, int64_t arg5,
+ int64_t arg6, int64_t arg7,
+ int64_t arg8);
typedef ObjectTriple (*SimulatorRuntimeTripleCall)(int64_t arg0, int64_t arg1,
int64_t arg2, int64_t arg3,
@@ -2022,14 +2023,19 @@ void Simulator::SoftwareInterrupt() {
// We first check if we met a call_rt_redirected.
if (instr_.InstructionBits() == rtCallRedirInstr) {
Redirection* redirection = Redirection::FromSwiInstruction(instr_.instr());
+
+ int64_t* stack_pointer = reinterpret_cast<int64_t*>(get_register(sp));
+
int64_t arg0 = get_register(a0);
int64_t arg1 = get_register(a1);
int64_t arg2 = get_register(a2);
int64_t arg3 = get_register(a3);
- int64_t arg4, arg5;
-
- arg4 = get_register(a4); // Abi n64 register a4.
- arg5 = get_register(a5); // Abi n64 register a5.
+ int64_t arg4 = get_register(a4);
+ int64_t arg5 = get_register(a5);
+ int64_t arg6 = get_register(a6);
+ int64_t arg7 = get_register(a7);
+ int64_t arg8 = stack_pointer[0];
+ STATIC_ASSERT(kMaxCParameters == 9);
bool fp_call =
(redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) ||
@@ -2224,14 +2230,13 @@ void Simulator::SoftwareInterrupt() {
PrintF(
"Call to host function at %p "
"args %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64
- " , %08" PRIx64 " , %08" PRIx64 " \n",
+ " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64
+ " , %08" PRIx64 " \n",
static_cast<void*>(FUNCTION_ADDR(target)), arg0, arg1, arg2, arg3,
- arg4, arg5);
+ arg4, arg5, arg6, arg7, arg8);
}
- // int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5);
- // set_register(v0, static_cast<int32_t>(result));
- // set_register(v1, static_cast<int32_t>(result >> 32));
- ObjectPair result = target(arg0, arg1, arg2, arg3, arg4, arg5);
+ ObjectPair result =
+ target(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8);
set_register(v0, (int64_t)(result.x));
set_register(v1, (int64_t)(result.y));
}
@@ -4032,73 +4037,101 @@ void Simulator::DecodeTypeRegisterSPECIAL2() {
void Simulator::DecodeTypeRegisterSPECIAL3() {
int64_t alu_out;
switch (instr_.FunctionFieldRaw()) {
- case INS: { // Mips64r2 instruction.
- // Interpret rd field as 5-bit msb of insert.
- uint16_t msb = rd_reg();
- // Interpret sa field as 5-bit lsb of insert.
- uint16_t lsb = sa();
- uint16_t size = msb - lsb + 1;
- uint64_t mask = (1ULL << size) - 1;
- alu_out = static_cast<int32_t>((rt_u() & ~(mask << lsb)) |
- ((rs_u() & mask) << lsb));
- SetResult(rt_reg(), alu_out);
- break;
- }
- case DINS: { // Mips64r2 instruction.
- // Interpret rd field as 5-bit msb of insert.
- uint16_t msb = rd_reg();
- // Interpret sa field as 5-bit lsb of insert.
- uint16_t lsb = sa();
- uint16_t size = msb - lsb + 1;
- uint64_t mask = (1ULL << size) - 1;
- alu_out = (rt_u() & ~(mask << lsb)) | ((rs_u() & mask) << lsb);
- SetResult(rt_reg(), alu_out);
- break;
- }
- case EXT: { // Mips64r2 instruction.
- // Interpret rd field as 5-bit msb of extract.
- uint16_t msb = rd_reg();
+ case EXT: { // Mips32r2 instruction.
+ // Interpret rd field as 5-bit msbd of extract.
+ uint16_t msbd = rd_reg();
// Interpret sa field as 5-bit lsb of extract.
uint16_t lsb = sa();
- uint16_t size = msb + 1;
+ uint16_t size = msbd + 1;
uint64_t mask = (1ULL << size) - 1;
alu_out = static_cast<int32_t>((rs_u() & (mask << lsb)) >> lsb);
SetResult(rt_reg(), alu_out);
break;
}
case DEXT: { // Mips64r2 instruction.
- // Interpret rd field as 5-bit msb of extract.
- uint16_t msb = rd_reg();
+ // Interpret rd field as 5-bit msbd of extract.
+ uint16_t msbd = rd_reg();
// Interpret sa field as 5-bit lsb of extract.
uint16_t lsb = sa();
- uint16_t size = msb + 1;
+ uint16_t size = msbd + 1;
uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
SetResult(rt_reg(), alu_out);
break;
}
case DEXTM: {
- // Interpret rd field as 5-bit msb of extract.
- uint16_t msb = rd_reg();
+ // Interpret rd field as 5-bit msbdminus32 of extract.
+ uint16_t msbdminus32 = rd_reg();
// Interpret sa field as 5-bit lsb of extract.
uint16_t lsb = sa();
- uint16_t size = msb + 33;
+ uint16_t size = msbdminus32 + 1 + 32;
uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
SetResult(rt_reg(), alu_out);
break;
}
case DEXTU: {
- // Interpret rd field as 5-bit msb of extract.
- uint16_t msb = rd_reg();
- // Interpret sa field as 5-bit lsb of extract.
+ // Interpret rd field as 5-bit msbd of extract.
+ uint16_t msbd = rd_reg();
+ // Interpret sa field as 5-bit lsbminus32 of extract and add 32 to get
+ // lsb.
uint16_t lsb = sa() + 32;
- uint16_t size = msb + 1;
+ uint16_t size = msbd + 1;
uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
SetResult(rt_reg(), alu_out);
break;
}
+ case INS: { // Mips32r2 instruction.
+ // Interpret rd field as 5-bit msb of insert.
+ uint16_t msb = rd_reg();
+ // Interpret sa field as 5-bit lsb of insert.
+ uint16_t lsb = sa();
+ uint16_t size = msb - lsb + 1;
+ uint64_t mask = (1ULL << size) - 1;
+ alu_out = static_cast<int32_t>((rt_u() & ~(mask << lsb)) |
+ ((rs_u() & mask) << lsb));
+ SetResult(rt_reg(), alu_out);
+ break;
+ }
+ case DINS: { // Mips64r2 instruction.
+ // Interpret rd field as 5-bit msb of insert.
+ uint16_t msb = rd_reg();
+ // Interpret sa field as 5-bit lsb of insert.
+ uint16_t lsb = sa();
+ uint16_t size = msb - lsb + 1;
+ uint64_t mask = (1ULL << size) - 1;
+ alu_out = (rt_u() & ~(mask << lsb)) | ((rs_u() & mask) << lsb);
+ SetResult(rt_reg(), alu_out);
+ break;
+ }
+ case DINSM: { // Mips64r2 instruction.
+ // Interpret rd field as 5-bit msbminus32 of insert.
+ uint16_t msbminus32 = rd_reg();
+ // Interpret sa field as 5-bit lsb of insert.
+ uint16_t lsb = sa();
+ uint16_t size = msbminus32 + 32 - lsb + 1;
+ uint64_t mask;
+ if (size < 64)
+ mask = (1ULL << size) - 1;
+ else
+ mask = std::numeric_limits<uint64_t>::max();
+ alu_out = (rt_u() & ~(mask << lsb)) | ((rs_u() & mask) << lsb);
+ SetResult(rt_reg(), alu_out);
+ break;
+ }
+ case DINSU: { // Mips64r2 instruction.
+ // Interpret rd field as 5-bit msbminus32 of insert.
+ uint16_t msbminus32 = rd_reg();
+ // Interpret rd field as 5-bit lsbminus32 of insert.
+ uint16_t lsbminus32 = sa();
+ uint16_t lsb = lsbminus32 + 32;
+ uint16_t size = msbminus32 + 32 - lsb + 1;
+ uint64_t mask = (1ULL << size) - 1;
+ alu_out = (rt_u() & ~(mask << lsb)) | ((rs_u() & mask) << lsb);
+ SetResult(rt_reg(), alu_out);
+ break;
+ }
case BSHFL: {
int32_t sa = instr_.SaFieldRaw() >> kSaShift;
switch (sa) {
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